RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 70
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RG82845 S L5YQ
Manufacturer Part Number
RG82845 S L5YQ
Description
Manufacturer
Intel
Datasheet
1.RG82845_S_L5YQ.pdf
(148 pages)
Specifications of RG82845 S L5YQ
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Register Description
3.5.30
70
Note: The address provided via ATTBASE is 4 KB aligned.
ATTBASE—Aperture Translation Table Base Register
(Device 0)
Address Offset:
Default Value:
Access:
Size:
This register provides the starting address of the Graphics Aperture Translation Table Base
located in the system memory. This value is used by the MCH Graphics Aperture address
translation logic (including the GTLB logic) to obtain the appropriate address translation entry
required during the translation of the aperture address into a corresponding physical system
memory address. The ATTBASE register may be dynamically changed.
31:12
11:0
Bit
Aperture Translation Table Base (TTABLE). This field contains a pointer to the base of the
translation table used to map memory space addresses in the aperture range to addresses in
system memory.
Note: It should be modified only when the GTLB has been disabled.
Reserved.
B8–BBh
0000_0000h
R/W
32 bits
Description
Intel
®
82845 MCH for SDR Datasheet
R
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