RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 111

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

5.2.3
Intel
64 Mb
64 Mb
128 Mb 2Meg x 16 x 4bks
128 Mb 4Meg x 8 x 4bks
256 Mb 4Meg x 16 x 4 bks
256 Mb 8Meg x 8 x 4 bks
512 Mb 8Meg x 16 x 4bks
512 Mb 16Meg x 8 x 4bks
Tech.
Table 14. Address Translation and Decoding
®
82845 MCH for SDR Datasheet
1Meg x 16 x 4 bks
2Meg x 8 x 4 bks
Configuration
R
Memory Address Translation and Decoding
The 845 MCH contains address decoders that translate the address received on the system bus or
the hub interface. Decoding and translation of these addresses vary with the four SDRAM types.
Also, the number of pages, page sizes, and densities supported vary with the type. In general, the
MCH supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM devices. The multiplexed
row/column address
signals. These addresses are derived from the system address bus as defined by Table 14 for
SDRAM devices.
Page size
Row size
128 MB
128 MB
256 MB
256 MB
512 MB
32 MB
64 MB
64 MB
16 KB
2 KB
4 KB
4 KB
8 KB
4 KB
8 KB
8 KB
Column /
12x10x2 Row
13x10x2 Row
13x10x2 Row
13x11x2 Row
12x8x2
12x9x2
12x9x2
13x9x2
Row /
Bank
to
the SDRAM memory array is provided by the SBS[1:0] and SMA[12:0]
Row
Row
Row
Row
Row
Col
Col
Col
Col
Col
Col
Col
Col
Col
Addr
24
25
25
26
26
27
27
28
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
11
13
13
14
13
14
14
14
12
12
12
13
12
13
13
15
26
27
27
27
24
24
24
26
24
26
26
26
13
AP
AP
AP
AP
AP
AP
AP
AP
13
25
25
25
25
25
25
25
14
14
14
24
12
14
24
12
24
12
24
12
15
15
11
15
11
15
11
15
11
15
11
15
11
28
11
16
10
16
10
16
10
16
10
16
10
16
10
16
10
16
10
23
23
23
23
23
23
23
23
9
9
9
9
9
9
9
9
Functional Description
22
22
22
22
22
22
22
22
8
8
8
8
8
8
8
8
21
21
21
21
21
21
21
21
7
7
7
7
7
7
7
7
20
20
20
20
20
20
20
20
6
6
6
6
6
6
6
6
19
19
19
19
19
19
19
19
5
5
5
5
5
5
5
5
18
18
18
18
18
18
18
18
4
4
4
4
4
4
4
4
111
17
17
17
17
17
17
17
17
3
3
3
3
3
3
3
3