RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 55

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.5.17
Intel
®
82845 MCH for SDR Datasheet
R
DRT—DRAM Timing Register (Device 0)
Offset:
Default:
Access:
Size:
31:19
18:16
15:11
10:9
Bit
8:6
5:4
3
2
1
0
Reserved.
DRAM Idle Timer. This field determines the number of clocks the DRAM controller will remain
in the idle state before it begins precharging all pages.
000 = infinite.
001 = 0 DRAM clocks
010 = 8 DRAM clocks
011 = 16 DRAM clocks
100 = 64 DRAM clocks
Others = Reserved
Reserved.
Activate to Precharge delay (tRAS). This bit controls the number of DRAM clocks for tRAS.
00 = 7 clocks
01 = 6 clocks
10 = 5 clocks
11 = Reserved
Reserved.
CAS# Latency (tCL). This bit controls the number of DRAM clocks between when a read
command is sampled by the SDRAMs and when the MCH samples read data from the
SDRAMs.
00 = Reserved
01 = 3 clocks
10 = 2 clocks
11 = Reserved
Reserved.
DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted between a
row activate command and a read or write command to that row.
0 = 3 DRAM clocks
1 = 2 DRAM clocks
Reserved.
DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted
between a row precharge command and an activate command to the same row.
0 = 3 DRAM clocks
1 = 2 DRAM clocks
78–7Bh
00000010h
R/W
32 bits
Description
Register Description
55