NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 5

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

Intel
Revision
NDA
-009
-010
-011
-012
-013
-014
-015
-016
-017
-018
-019
-020
-021
®
ICH8 Family Specification Update
• Added Mobile ICH8M products (82801HBM ICH8M, and 82801HEM ICH8M-E I/O
• Removed items as this information has been added to the datasheet, Revision -003:
• Added Errata 14-15
• Added:
• Added:
• Updated Device ID and Revision ID table to include information on ICH8M B1 stepping
• Added:
• This revision was for administrative management only and was not released
• Added:
• Updated Identification Information Section to include top marking and Device ID for
• Added:
• Added:
• Added:
• Added:
• Added:
• Added:
• Document Change: 12 - Correct section 9.1.21 Bits 15:2 definition
• Document Change: 13 - Correct Figure 20 and Figure 21 Ballout information
• Updated Document Change 13 - Correct Figure 20 and Figure 21 Ballout information
• Added:
• Document Change: 14 - Correct section 11.1.43 bit 0 definition
Controller Hubs)
ICH8M B2 stepping
— Specification Changes 1-4
— Specification Clarifications 1-12
— Documentation Changes 2-23
— Errata: 16-
— Specification Changes:1-
— Specification Clarifications: 1-RTC Register A Clarification, 2-
— Document Changes: 1-
— Errata:
— Specification Changes:
— Specification Clarifications: 3-
— Document Changes: 2
— Errata: 22-SMBus Host Controller May Hang, 23-SATA Gen1 Initialization / LPM
— Specification Changes: 4-Addition of EHCI Parity Error Response.
— Document Changes: 4-
— Errata: 24-
— Document Changes: 6-
— Specification Clarifications: 4-
— Document Changes:9-
— Document Change: 10-Add ballout AH19(VSS) to Table 147
— Errata: 25-Intel® I/O Controller Hub 8 (ICH8) Family PCI Express Function Disable
— Document Change: 11-Correct Section 5.13.7.5 Sx-G3-Sx, Handling Power Failures
Note: Documentation Change 1 (Revision ID and Device ID information) was moved
to the Identification Information section
GbE Packet Buffer Writing Error, 18-ICH8 THRM Polarity on SMBus.
Low Time Clarification.
USB 2.0 V
Support for USB Wake from S5.
Connectivity Clarification
Erratum.
Corrections
Erratum
Timer, 8-Timing Figure Clarification
regarding possible wake events following a power failure
19-AHCI Reset and MSI Request, 20-PET Alerts on SMBus, 21-High-speed
High Speed (HS) USB 2.0 D+ and D- maximum Driven Signal Level, 17-
ICH8M B2 Stepping Gigabit Ethernet Controller RID with CRID Enabled
HSOH
-PWROK Description Correction, 3-SMBus/SMLink
GPIO_USE_SEL Override Register Description Correction
2-USB 2.0 Power Management Description, 3-Removing
Bit 0 Function Disable Register Correction.
CK_PWRGD Pin State Correction, 5-SATA Registers
SATA Interlock Switch State (ISS) Bit Clarification, 7-HPET
SPI Specification Addition.
USB UHCI Run/Stop Bit Clarification
t290 and t294 Clarification
Description
GLANCLK High Time/
May 2007
September 2007
November 2007
April 2008
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May 2010
June 2010
Date
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