NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 15

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

Implication: No functional implications known. Writes of values corresponding to the D2 and D1
Workaround:Software should not write unsupported power state values (i.e., 10b or 01b) to the
Status:
6.
Problem:
Implication: Integrated LAN does not provide support for WOL after a G3 to S5 transition until
Implication: Platform must briefly transition to S0 and then may return to S5. BIOS workaround
Status:
7.
Problem:
Note:
Implication: The LAN DMA engine error may cause transmitted data from the ICH8 integrated LAN
Note:
Workaround:Update ICH8 NVM to version 1.1 or later to cover all known failures. Update Intel LAN
Note:
Status:
8.
Problem:
Intel
• An internal DMA buffer is full
• A read request directly follows a write request to the DMA buffer
• The next request packet size is larger than 128 Bytes
• Alignment of DMA buffer read and write pointers
• NVM Change: Program bit 1 of Word 0x13h to 0 in the ICH8 GbE NVM image. This is implemented
• Through extensive validation and focused testing, Intel has not observed failures with bit 1 of
®
in NVM version 1.1 and later.
Word 0x13h set to 0 in the ICH8 NVM image. To protect against a theoretical case where the issue
could occur even when the NVM image is updated, Intel recommends a driver update that
customers should implement as soon as feasible.
ICH8 Family Specification Update
ICH8 PCI Express root port PCI Power Management Capabilities Registers (D28:F0/F1/
F2/F3/F4/F5:A2h) do not claim support of D2 and D1 power states.
states (i.e., 10b or 01b) do not cause behavioral changes within the ICH8, but the value
is displayed in the Power State bit field.
Power State bit field of the Power Management Control and Status register.
No Fix. For steppings affected, see the Summary Tables of Changes.
Intel ICH8 LAN APM Wakeup After G3
The APM Wakeup enable bit, which controls if the ICH8 supports Wake on LAN (WOL) in
response to a magic packet in S5, is in a region of the LAN NVM (Nonvolatile Memory)
that is read only after PLTRST# deasserts when the system boots to S0.
PLTRST# deasserts because the default state of the APM Wakeup enable bit is disabled.
Additionally, because WOL is disabled, a LAN link will not be established and LAN will
remain in the off state until PLTRST# deasserts.
available; Contact your Intel field representative for the latest BIOS information
No Fix (Desktop Only). For steppings affected, see the Summary Tables of Changes.
Intel ICH8 Integrated LAN DMA Error
The ICH8 integrated LAN DMA engine may experience an internal error on some
systems where a specific alignment of internal logic clock domains may exist and when
all of the following additional conditions are met:
Issue has only been reproduced under synthetic lab conditions.
to be incorrect.
Data error occurs before CRC calculation; erroneous data cannot be detected by CRC
check by LAN interface partner.
driver to Trout Lake version 1.1 Build 125734 or later as soon as feasible to cover both
all known and theoretical failures.
If able to immediately implement driver workaround, NVM change is not required.
No Fix. (Desktop Only). For steppings affected, see the Summary Tables of Changes.
Intel
The ICH8 PCI Express root ports’ Upstream Link Base Address (ULBA) Register
(D28:F0/F1/F2/F3/F4/F5:198h) bit 0 mirrors the value of bit 0 in the ICH8 RCBA
®
ICH8 PCI Express* Upstream Link Base Address Register Bit 0
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