NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 29

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

11.
The AFTER_G3 bit provides the ability to program whether or not the system should boot once power
returns after a power loss event. If the policy is to not boot, the system remains in an S5 state
(unless previously in S4).
power failure.
RSMRST# going low and enabling by default, the enable bits reside in the RCT well or the wake event
is always enabled.
The ICH8 monitors both PWROK and RSMRST# to detect for power failures. If PWROK
goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss.
PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
12.
Intel
®
1.PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3 state),
the PWRBTN_STS bit is reset. When the ICH8 exits G3 after power returns (RSMRST# goes high),
the PWRBTN# signal is already high (because V
and the PWRBTN_STS bit is 0.
2.RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event,
it is important to keep this signal powered during the power loss event. If this signal goes low
(active), when power returns the RI_STS bit is set and the system interprets that as a wake
event.
3.RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like
PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
4.PCI Express Wake# Signal: The PCIEXPWAK_DIS bit is cleared by RSMRST#
going low enabling PCI Express Ports to wake the platform after a power loss. The
PCIEXPWAK_STS bit is also cleared when RSMRST# goes low.
5.PME_B0: PME_B0_EN is in the RTC Well and is preserved after a power loss. The PME_B0_STS
bit is also cleared when RSMRST# goes low.
6.PME: PME_EN: is in the RTC Well and is preserved after a power loss. The PME_STS bit is also
cleared when RSMRST# goes low.
7.Host SMBUS: SMBALERT# or Slave Wake message is always enabled as Wake Event
8.ME Non-Maskable Wake: Always enabled as Wake Event.
ICH8 Family Specification Update
Correct section 9.1.21 GEN1_DEC-LPC I/F Generic Decode Range 1 Register in the
Datasheet
Correct section 5.13.7.5 Sx-G3-Sx, Handling Power Failures regarding
possible wake events following a power failure
Correct section 5.13.7.5 Sx-G3-Sx, Handling Power Failures in the Datasheet.
Section 5.13.7.5 Sx-G3-Sx, Handling Power Failures§
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
Correct section 9.1.21 Bits 15:2 definition
The following wake events can wake the system following a power loss by either
There are only three possible events that will wake the system after a
CC
-standby goes high before RSMRST# goes high)
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