NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 18

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

Implication: May cause High Speed (HS) USB 2.0 devices to be unrecognized by OS or may not be
Workaround:None.
Status:
17.
Problem:
Implication: Incorrect data may be transmitted from the ICH8 integrated LAN controller
Workaround:Driver workaround available
Status:
18.
Problem:
Implication: If the THRM#_POL bit is set to high, an external SMBus master reading the BTI
Workaround:None.
Status:
19.
Problem:
Implication: Issue has only been observed in a synthetic test environment. Unexpected system
Workaround:Prior to performing an HBA reset, software should disable AHCI interrupts by writing a
Intel
• The receiver is pseudo differential design
• The receiver is not able to ignore SE1 (single-ended) state
• Use released driver version 9.7.32.0 or later for NDIS 6
• Use released driver version 9.7.34.0 or later for NDIS 5.x
®
ICH8 Family Specification Update
Note: Intel has only observed this issue with a motherboard down HS USB 2.0 device using
Note: Issue has only been reproduced under synthetic lab conditions. In addition, two
Note: The erroneous data will be detected by the receiver’s checksum calculation and will not
Note: Intel
readable/writable if the following two conditions are met:
pseudo differential design. This issue will not affect HS USB 2.0 devices with
complementary differential design or Low Speed (LS) and Full Speed (FS) devices
No Fix. For steppings affected, see the Summary Tables of Changes.
ICH8 GbE Packet Buffer Writing Error
With System Defense enabled, the ICH8 integrated LAN’s Packet Buffer writing
mechanism may encounter an internal error when there are two consecutive write
requests to the same address of the Packet Buffer.
consecutive write requests to the same address in the Packet Buffer do not happen
under typical operating conditions.
get to the application level. The packet will be either re-transmitted (TCP protocol) or
dropped (UCP protocol).
No Fix. For steppings affected, see the Summary Tables of Changes.
ICH8 THRM Polarity on SMBus
When THRM#_POL (PMBASE+42h:bit0) is set to high, the THRM# pin state as reported
to the SMBus TCO unit is logically inverted.
Temperature Event status will not receive the correct state of the THRM# pin. The
value will be logically inverted. If THRM#_POL set to low, value is correct.
No Fix. For steppings affected, see the Summary Tables of Changes.
AHCI Reset and MSI Request
If the ICH8 AHCI SATA controller receives a HBA reset while MSI interrupts are
enabled, a boundary condition exists where the ICH8 SATA controller may respond to a
non-posted request that is intended for another ICH8 function.
behavior may occur. System implication may vary depending on the non-posted
request that is fulfilled.
Linux may enable MSIs and use the HBA reset command. No other third-party
software known to utilize MSI interrupts.
‘0’ to Interrupt Enable bit (ABAR+04h, bit 1) and then perform a read to the AHCI GHC
register (ABAR+04h).
®
Matrix Storage Manager AHCI driver does not use the HBA reset command.
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