NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 22

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

3.
Support for USB wake from S5 is removed from the Datasheet as indicated below.
a. Update Intel
USB 2.0
b. Update Table 5-31 as follows:
Table 5-31. Causes of Wake Events
4.
Parity Error Response is supported by the ICH8 Enhanced Host Controller (EHC). The following
changes apply to Section 20.1.3 of the EDS and Section 15.1.3 of the Datasheet to reflect the added
capability.
Intel
®
ICH8 Family Specification Update
Removing Support for USB Wake from S5
Addition of EHCI Parity Error Response
Classic USB
®
ICH8 Features page of the Datasheet as follows:
—NEW: Up to five UHCI Host Controllers, supporting ten external ports
—NEW: Up to two EHCI Host Controllers that support ten external ports
—NEW: Per-Port-Disable Capability
—NEW: Includes up to two USB 2.0 High-speed Debug Ports
—Supports wake-up from sleeping states
—Supports legacy Keyboard/Mouse software
Cause
8
6
SERR# Enable (SERR_EN) — R/W
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host Controller (EHC) is capable of generating (internally)
SERR# in the following cases:
-
DMA -initiated memory reads on DMI (and subsequently on its internal
interface).
- When it detects an address or command parity error and the Parity Error
Response bit is set.
- When it detects a data parity error (when the data is going into the EHC) and
the Parity Error Response bit is set.
Parity Error Response (PER) — R/W.
0 = The EHC is not checking for correct parity (on its internal interface).
1 = The EHC is checking for correct parity (on its internal interface) and halt
NOTE: If the EHC detects bad parity on the address or command phases when
the bit is set to 1, the host controller does not take the cycle. It halts the host
controller (if currently not halted) and sets the Host System Error bit in the
USBSTS register. This applies to both requests and completions from the
system interface.
This bit must be set in order for the parity errors to generate SERR#.
When it receives a completion status other than “successful” for one of its
Wake From
States Can
operation when bad parity is detected during the data phase.
S1–S4
Set USB1_EN, USB 2_EN, USB3_EN, USB4_EN, and
USB5_EN, bits in GPE0_EN register
S1–S4
How Enabled
22