NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 16

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

Implication: No functional implications known.
Workaround:None.
Status:
9.
Problem:
Implication: The SST controller may not be able to access the SST device that utilizes sampling
Workaround:If SST supported device samples the bus at 0.56xTBIT or above then the board
Status:
10.
Problem:
Implication: There is no known impact to platform functionality. The platform may flag a failure for
Workaround:None.
Status:
11.
Problem:
Implication: A USB LS/FS device that wakes the system may stop functioning after the system
Note:
Intel
®
ICH8 Family Specification Update
register (D31:F0:F0h). During normal system operation, bit 0 of the RCBA register is
set to 1. This results in bit 0 of the ULBA also being set to 1. The PCI Express specifi-
cation, rev 1.1, requires that bit 0 of the ULBA be 0.
No Fix. For steppings affected, see the Summary Tables of Changes.
Intel
The ICH8 may violate the SST TH0 and TH1 minimum specification when driving the
SST bus.
times above 0.56xTBIT.
Note: a SST-spec compliant device can utilize sampling times above 0.56xTBIT and up
to 0.60xTBIT
designer may implement a capacitor to ground on the SST signal. The value of the
capacitor can be determined using the following formula:
Cap
1)*SSTDevC]
Where:
typ, 170 pF max)
3.8 pF max)
Note:
No Fix. For steppings affected, see the Summary Tables of Changes.
ICH8 PCI Express* Endpoint L0/L1 Acceptable Latency Bits
The ICH8 implements the PCI Express* Endpoint L0/L1 Acceptable Latency bits (bits
[8:6] and [11:9] in Device Capabilities Register) as RO with the value of ‘1’. The PCI
Express Specification rev 1.1 requires the bits to be RO with the value of ‘0’.
each bit field with Microsoft Vista* Compliance test.
Intel is working with Microsoft to get contingencies for the failures.
No Fix. For steppings affected, see the Summary Tables of Changes.
ICH8 USB K-State Reflection on Resume
Upon resuming from a USB wake-up event from S3-S4, the ICH8 USB host controller
(UHCI or EHCI) may not reflect the resume K-state sent by the USB device back onto
the bus as required by the USB 2.0 Specification.
resumes from S3-S4.
A USB HS device that wakes the system is not impacted as the USB driver will reset the
port when the device is not responding after resume.
®
Value
ICH8 Simple Serial Transport (SST) TH0 and TH1 Timing
SSTSysCReg = SST System Capacitance Requirement (100 pF min, 140 pF
MBLength = Total SST trace length on the motherboard (inch)
MBTraceC = Motherboard Trace Capacitance per inch (2.6 pF min, 3.2 pF typ,
NumberSSTDev = Total number of SST devices implemented on motherboard
SSTDevC = Capacitance of SST device (6 pF min, 8 pF typ, 10pF max)
Capacitor value range can be determined using min and max values
Do not mix and match min, typ and max values in the calculation
Recommended capacitor value can be obtained using the typ values
=
(SSTSysCReq)
–
(MBLength*MBTraceC)
–
[(NumberSSTDev
16
+