NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 24

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

Document Changes
1.
The following change applies to bit 0 of the Function Disable register in Section 7.1.71 of the
Datahshet.
2.
The following change applies to Section 5.13.11.3 of the Datasheet.
The PWROK input should go active no sooner than 99 ms after the core supply voltages become valid.
PWROK must not glitch, even if RSMRST# is low.
3.
The following change applies to the 4th paragraph in Section 5.20.1 of the Datasheet.
The ICH8 supports the System Management Bus (SMBus) Specification, Version 2.0. Slave
functionality, including the Host Notify protocol, is available on the SMBus pins. The SMLink and
SMBus signals
5.14.2 for more
4.
The state of CK_PWRGD pin during S3 and S4/S5 is changed to ‘Low’ instead of ‘High’ in Table 33 and
Table 34 of the Datasheet.
5.
1. Section 12.2.3.1, 12.2.3.2, 12.2.3.3, 13.2.3.1, 13.2.3.2, and 13.2.3.3 are removed from the
Datasheet.
2. The following registers will be added as new sections after both Section 12.3.2 and Section 13.3.2
of the Datasheet.
PxSSTS—Serial ATA Status Register (D31:F2)
Address Offset:
Default Value:
SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state of the
interface and host. The ICH8 updates it continuously and asynchronously. When the ICH8 transmits a
COMRESET to the device, this register is updated to its reset values.
Intel
®
ICH8 Family Specification Update
Bit 0 Function Disable Register Correction
PWROK Description Correction
SMBus/SMLink Connectivity Clarification
CK_PWRGD Pin State Correction
SATA Registers Corrections
can be tied together externally depending on the TCO mode used. Refer to Section
31:12
details.
Bit
00000000h
0
Reserved
BIOS must set this bit to 1b.
Attribute:
Size:
Description
RO
32 bits
24