PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 395

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

INDEX
A
A/D ................................................................................... 259
Absolute Maximum Ratings ............................................. 349
AC (Timing) Characteristics ............................................. 364
ACKSTAT ........................................................................ 213
ACKSTAT Status Flag ..................................................... 213
ADCAL Bit ........................................................................ 267
ADCON0 Register ............................................................ 259
ADCON1 Register ............................................................ 259
ADCON2 Register ............................................................ 259
ADDFSR .......................................................................... 342
ADDLW ............................................................................ 305
Addressable Universal Synchronous Asynchronous
ADDULNK ........................................................................ 342
ADDWF ............................................................................ 305
ADDWFC ......................................................................... 306
ADRESH Register ............................................................ 259
ADRESL Register .................................................... 259, 262
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 306
ANDWF ............................................................................ 307
Assembler
AUSART
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A/D Converter Interrupt, Configuring ....................... 263
Acquisition Requirements ........................................ 264
ADCAL Bit ................................................................ 267
ADCON0 Register .................................................... 259
ADCON1 Register .................................................... 259
ADCON2 Register .................................................... 259
ADRESH Register ............................................ 259, 262
ADRESL Register .................................................... 259
Analog Port Pins, Configuring .................................. 265
Associated Registers ............................................... 267
Automatic Acquisition Time ...................................... 265
Configuring the Module ............................................ 263
Conversion Clock (T
Conversion Requirements ....................................... 385
Conversion Status (GO/DONE Bit) .......................... 262
Conversions ............................................................. 266
Converter Calibration ............................................... 267
Converter Characteristics ........................................ 384
Operation in Power-Managed Modes ...................... 267
Special Event Trigger (CCP2) .................................. 266
Use of the CCP2 Trigger .......................................... 266
Load Conditions for Device Timing
Parameter Symbology ............................................. 364
Temperature and Voltage Specifications ................. 365
Timing Conditions .................................................... 365
GO/DONE Bit ........................................................... 262
Receiver Transmitter (AUSART). See AUSART.
MPASM Assembler .................................................. 296
Asynchronous Mode ................................................ 250
Specifications ................................................... 365
Associated Registers, Receive ........................ 253
Associated Registers, Transmit ....................... 251
Receiver ........................................................... 252
Reception Setup .............................................. 252
Setting up 9-Bit Mode with Address Detect ..... 252
Transmission Setup ......................................... 250
Transmitter ....................................................... 250
Reception with Address Detect
Enable Setup ................................... 252
AD
) ........................................... 265
PIC18F85J11 FAMILY
Auto-Wake-up on Sync Break Character ......................... 237
B
Baud Rate Generator ...................................................... 209
BC .................................................................................... 307
BCF ................................................................................. 308
BF .................................................................................... 213
BF Status Flag ................................................................. 213
Block Diagrams
Baud Rate Generator (BRG) ................................... 248
Control Registers ..................................................... 245
Synchronous Master Mode ...................................... 254
Synchronous Slave Mode ........................................ 257
16-Bit Byte Select Mode .......................................... 105
16-Bit Byte Write Mode ............................................ 103
16-Bit Word Write Mode .......................................... 104
8-Bit Multiplexed Mode ............................................ 107
A/D ........................................................................... 262
Analog Input Model .................................................. 263
AUSART Receive .................................................... 252
AUSART Transmit ................................................... 250
Baud Rate Generator .............................................. 209
Capture Mode Operation ......................................... 172
Comparator Analog Input Model .............................. 273
Comparator I/O Operating Modes ........................... 270
Comparator Output .................................................. 272
Comparator Voltage Reference ............................... 276
Comparator Voltage Reference Output
Compare Mode Operation ....................................... 173
Connections for On-Chip Voltage Regulator ........... 288
Device Clock .............................................................. 35
EUSART Receive .................................................... 235
EUSART Transmit ................................................... 233
External Power-on Reset Circuit
Fail-Safe Clock Monitor ........................................... 291
Generic I/O Port Operation ...................................... 129
Interrupt Logic .......................................................... 114
MSSP (I
MSSP (I
MSSP (SPI Mode) ................................................... 179
On-Chip Reset Circuit ................................................ 51
PIC18F6XJ11 ............................................................ 12
PIC18F8XJ11 ............................................................ 13
Associated Registers ....................................... 248
Baud Rate Error, Calculating ........................... 248
Baud Rates, Asynchronous Modes ................. 249
High Baud Rate Select (BRGH Bit) ................. 248
Operation in Power-Managed Modes .............. 248
Sampling ......................................................... 248
Associated Registers, Receive ........................ 256
Associated Registers, Transmit ....................... 255
Reception ........................................................ 256
Reception Setup .............................................. 256
Transmission ................................................... 254
Transmission Setup ......................................... 254
Associated Registers, Receive ........................ 258
Associated Registers, Transmit ....................... 257
Reception ........................................................ 258
Reception Setup .............................................. 258
Transmission ................................................... 257
Transmission Setup ......................................... 257
Buffer Example ................................................ 277
(Slow V
2
2
C Master Mode) ........................................ 207
C Mode) .................................................... 188
DD
Power-up) ........................................ 53
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