PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 248

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
19.2
The BRG is a dedicated, 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
The SPBRG2 register controls the period of a
free-running timer. In Asynchronous mode, bit BRGH
(TXSTA<2>) also controls the baud rate. In Synchro-
nous mode, BRGH is ignored. Table 19-1 shows the
formula for computation of the baud rate for different
AUSART modes, which only apply in Master mode
(internally generated clock).
Given the desired baud rate and F
ger value for the SPBRG2 register can be calculated
using the formulas in Table 19-1. From this, the error in
baud rate can be determined. An example calculation is
shown in Example 19-1. Typical baud rates and error
values for the various Asynchronous modes are shown
TABLE 19-1:
EXAMPLE 19-1:
TABLE 19-2:
DS39774D-page 248
Legend: x = Don’t care, n = Value of SPBRG2 register
TXSTA2
RCSTA2
SPBRG2
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate
Solving for SPBRG2:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
Name
SYNC
Configuration Bits
0
0
1
AUSART Baud Rate Generator
(BRG)
AUSART Baud Rate Generator Register
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
X
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
OSC
BRGH
CALCULATING BAUD RATE ERROR
= F
= ((F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
0
1
x
OSC
Bit 6
OSC
TX9
RX9
/(64 ([SPBRG2] + 1))
/Desired Baud Rate)/64) – 1
OSC
, the nearest inte-
SREN
TXEN
Bit 5
BRG/AUSART Mode
Asynchronous
Asynchronous
Synchronous
CREN
SYNC
Bit 4
ADDEN
in Table 19-2. It may be advantageous to use the high
baud rate (BRGH = 1) to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
19.2.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
19.2.2
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or low level
is present at the RX2 pin.
Bit 3
—
BRGH
FERR
Bit 2
OPERATION IN POWER-MANAGED
MODES
SAMPLING
OERR
TRMT
Baud Rate Formula
Bit 1
 2010 Microchip Technology Inc.
F
F
F
OSC
OSC
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
RX9D
TX9D
Bit 0
Values on
Reset
page
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