PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 192

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
REGISTER 17-6:
DS39774D-page 192
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-2
bit 1
bit 0
Note 1:
R/W-0
GCEN
If the I
writes to the SSPBUF are disabled).
GCEN: General Call Enable bit
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
ADMSK<5:2>: Slave Address Mask Select bits
1 = Masking of corresponding bits of SSPADD enabled
0 = Masking of corresponding bits of SSPADD disabled
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Address mode:
1 = Masking of SSPADD<1> only is enabled
0 = Masking of SSPADD<1> only is disabled
In 10-Bit Address mode:
1 = Masking of SSPADD<1:0> is enabled
0 = Masking of SSPADD<1:0> is disabled
SEN: Stretch Enable bit
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
ACKSTAT
2
R/W-0
C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
SSPCON2: MSSP CONTROL REGISTER 2 (I
W = Writable bit
‘1’ = Bit is set
ADMSK5
R/W-0
(1)
ADMSK4
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADMSK3
R/W-0
2
C™ SLAVE MODE)
ADMSK2
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
ADMSK1
R/W-0
SEN
R/W-0
(1)
bit 0