PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 385

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

FIGURE 26-23:
TABLE 26-26: A/D CONVERSION REQUIREMENTS
 2010 Microchip Technology Inc.
130
131
132
135
137
Note 1:
Param
No.
Note 1:
A/D DATA
SAMPLE
2:
3:
4:
A/D CLK
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
DIS
2:
GO
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
Q4
If the A/D clock source is selected as RC, a time of T
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D Clock Period
Conversion Time
(not including acquisition time)
Acquisition Time
Switching Time from Convert  Sample
Discharge Time
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
9
(3)
to V
SS
8
or V
OLD_DATA
7
SS
(2)
to V
SAMPLING STOPPED
. . .
CY
DD
is added before the A/D clock starts. This allows the SLEEP instruction
). The source impedance (R
CY
. . .
130
131
PIC18F85J11 FAMILY
cycle.
Min
0.7
1.4
0.2
—
11
—
2
(Note 4)
25.0
Max
12
—
—
—
1
1
(1)
Units
T
µs
µs
µs
µs
AD
0
S
) on the input channels is 50.
T
A/D RC mode
-40C to +85C
OSC
AD
based, V
clock divider.
DONE
NEW_DATA
Conditions
DS39774D-page 385
T
CY
(Note 1)
REF
 3.0V