PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 329
PIC18F64J11T-I/PT
Manufacturer Part Number
PIC18F64J11T-I/PT
Description
16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(408 pages)
3.PIC18F63J11-IPT.pdf
(4 pages)
4.PIC18F63J11-IPT.pdf
(36 pages)
5.PIC18F63J11-IPT.pdf
(10 pages)
6.PIC18F63J11-IPT.pdf
(6 pages)
Specifications of PIC18F64J11T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F64J11T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F64J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F63J11-IPT PDF datasheet #3
- PIC18F63J11-IPT PDF datasheet #4
- PIC18F63J11-IPT PDF datasheet #5
- PIC18F63J11-IPT PDF datasheet #6
- Current page: 329 of 408
- Download datasheet (4Mb)
RCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC =
PC =
TOS =
Q1
Read literal
Address (HERE)
Address (Jump)
Address (HERE + 2)
PUSH PC
operation
Relative Call
RCALL n
-1024 n 1023
(PC) + 2 TOS,
(PC) + 2 + 2n PC
None
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number, ‘2n’, to the PC. Since the PC
will have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1
2
HERE
to stack
1101
No
Q2
‘n’
RCALL Jump
1nnn
operation
Process
Data
No
Q3
nnnn
Write to PC
operation
No
Q4
nnnn
PIC18F85J11 FAMILY
RESET
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
After Instruction
Decode
Registers =
Flags*
Q1
=
Reset
RESET
None
Reset all registers and flags that are
affected by a MCLR Reset.
All
This instruction provides a way to
execute a MCLR Reset in software.
1
1
RESET
Reset
Start
0000
Q2
Reset Value
Reset Value
0000
operation
No
Q3
DS39774D-page 329
1111
operation
No
Q4
1111
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