PIC18F43K20-E/MV Microchip Technology, PIC18F43K20-E/MV Datasheet - Page 451

• Manufacturer Part Number: PIC18F43K20-E/MV
• Description: 8KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TUB
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F43K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

Timer1 .............................................................................. 159
Timer2 .............................................................................. 167
Timer3 .............................................................................. 169
Timing Diagrams
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16-Bit Read/Write Mode ........................................... 162
Associated Registers ............................................... 165
Asynchronous Counter Mode .................................. 161
Interrupt .................................................................... 163
Operation ................................................................. 160
Oscillator .......................................................... 159, 162
Oscillator Layout Considerations ............................. 163
Overflow Interrupt .................................................... 159
Prescaler .................................................................. 161
Resetting, Using the CCP Special Event Trigger ..... 163
Special Event Trigger (ECCP) ................................. 174
TMR1H Register ...................................................... 159
TMR1L Register ....................................................... 159
Use as a Real-Time Clock ....................................... 164
Associated Registers ............................................... 168
Interrupt .................................................................... 168
Operation ................................................................. 167
Output ...................................................................... 168
16-Bit Read/Write Mode ........................................... 171
Associated Registers ............................................... 172
Operation ................................................................. 170
Oscillator .......................................................... 169, 171
Overflow Interrupt ............................................ 169, 171
Special Event Trigger (CCP) .................................... 172
TMR3H Register ...................................................... 169
TMR3L Register ....................................................... 169
A/D Conversion ........................................................ 402
Acknowledge Sequence .......................................... 228
Asynchronous Reception ......................................... 245
Asynchronous Transmission .................................... 240
Asynchronous Transmission (Back to Back) ........... 241
Auto Wake-up Bit (WUE) During Normal
Auto Wake-up Bit (WUE) During Sleep ................... 255
Automatic Baud Rate Calculator .............................. 254
Baud Rate Generator with Clock Arbitration ............ 222
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 388
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) .... 231
Bus Collision During a Stop Condition (Case 1) ...... 234
Bus Collision During a Stop Condition (Case 2) ...... 234
Bus Collision During Start Condition (SDA only) ..... 230
Bus Collision for Transmit and Acknowledge ........... 229
Capture/Compare/PWM (CCP) ................................ 390
CLKO and I/O .......................................................... 387
Clock Synchronization ............................................. 215
Clock/Instruction Cycle .............................................. 69
Comparator Output .................................................. 279
Example SPI Master Mode (CKE = 0) ..................... 392
Example SPI Master Mode (CKE = 1) ..................... 393
Example SPI Slave Mode (CKE = 0) ....................... 394
Example SPI Slave Mode (CKE = 1) ....................... 395
External Clock (All Modes except PLL) .................... 384
Fail-Safe Clock Monitor (FSCM) ................................ 41
First Start Bit Timing ................................................ 223
Reading and Writing ........................................ 161
Operation ......................................................... 255
Start Condition ................................................. 231
(Case 1) ........................................................... 232
(Case 2) ........................................................... 233
Timing Diagrams and Specifications ............................... 384
PIC18F2XK20/4XK20
Full-Bridge PWM Output .......................................... 180
Half-Bridge PWM Output ................................. 178, 185
High/Low-Voltage Detect Characteristics ................ 382
High/Low-Voltage Detect Operation
High/Low-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
Internal Oscillator Switch Timing ............................... 39
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4XK20) ......................... 391
Parallel Slave Port (PSP) Read ............................... 140
Parallel Slave Port (PSP) Write ............................... 140
PWM Auto-shutdown
PWM Direction Change ........................................... 181
PWM Direction Change at Near 100% Duty Cycle .. 182
PWM Output (Active-High) ...................................... 176
PWM Output (Active-Low) ....................................... 177
Repeat Start Condition ............................................ 224
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 256
Slave Synchronization ............................................. 199
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 198
SPI Mode (Slave Mode, CKE = 0) ........................... 200
SPI Mode (Slave Mode, CKE = 1) ........................... 200
Synchronous Reception (Master Mode, SREN) ...... 261
Synchronous Transmission ..................................... 258
Synchronous Transmission (Through TXEN) .......... 258
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock .......................... 389
Timer1 Incrementing Edge ...................................... 161
Transition for Entry to Sleep Mode ............................ 46
Transition for Wake from Sleep (HSPLL) .................. 46
Transition Timing for Entry to Idle Mode .................... 47
Transition Timing for Wake from Idle to
USART Synchronous Receive (Master/Slave) ........ 400
USART Synchronous Transmission
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 396
C Bus Start/Stop Bits ............................................ 396
C Master Mode (7 or 10-Bit Transmission) ........... 226
C Master Mode (7-Bit Reception) ......................... 227
C Slave Mode (10-Bit Reception, SEN = 0) .......... 211
C Slave Mode (10-Bit Reception, SEN = 1) .......... 217
C Slave Mode (10-Bit Transmission) .................... 212
C Slave Mode (7-bit Reception, SEN = 0) ............ 209
C Slave Mode (7-Bit Reception, SEN = 1) ............ 216
C Slave Mode (7-Bit Transmission) ...................... 210
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 228
(VDIRMAG = 0) ............................................... 295
(VDIRMAG = 1) ............................................... 296
Sequence (7 or 10-Bit Address Mode) ............ 218
Auto-restart Enabled ........................................ 184
Firmware Restart ............................................. 184
V
(MCLR Tied to V
Not Tied to V
Not Tied to V
Tied to V
Run Mode .......................................................... 47
(Master/Slave) ................................................. 400
Timer (OST), Power-up Timer (PWRT) .......... 388
DD
Rise > T
2
2
DD
C Bus Data ....................................... 398
C Bus Start/Stop Bits ........................ 398
, V
PWRT
DD
DD
DD
, Case 1) ................................... 56
, Case 2) ................................... 56
DD
Rise < T
) ............................................ 57
) .......................................... 57
PWRT
DD
DS41303G-page 451
,
) ....................... 56