PIC18F43K20-E/MV Microchip Technology, PIC18F43K20-E/MV Datasheet - Page 269

• Manufacturer Part Number: PIC18F43K20-E/MV
• Description: 8KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TUB
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F43K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

19.2.2
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH:ADRESL registers with new
19.2.3
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged after every
sample. This feature helps to optimize the unity-gain
amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
19.2.4
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared by software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion.
19.2.5
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, the currently selected
channel is reconnected to the charge holding capacitor
commencing the next acquisition.
19.2.6
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D F
clock source should be selected.
 2010 Microchip Technology Inc.
conversion result
Note:
AD
wait is required before the next acquisition can
COMPLETION OF A CONVERSION
DISCHARGE
TERMINATING A CONVERSION
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
DELAY BETWEEN CONVERSIONS
ADC OPERATION IN POWER-
MANAGED MODES
RC
19.2.7
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the F
option. When the F
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
F
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
19.2.8
The CCP2 Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 or Timer3 counter resets to zero.
Using the Special Event Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
See Section 11.3.4 “Special Event Trigger” for more
information.
PIC18F2XK20/4XK20
RC
, a SLEEP instruction causes the present conver-
ADC OPERATION DURING SLEEP
SPECIAL EVENT TRIGGER
RC
clock source is selected, the
DS41303G-page 269
RC