PIC18F43K20-E/MV Microchip Technology, PIC18F43K20-E/MV Datasheet - Page 194

• Manufacturer Part Number: PIC18F43K20-E/MV
• Description: 8KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TUB
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F43K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC18F2XK20/4XK20
17.3.1
The MSSP module has four registers for SPI mode
operation. These are:
• SSPCON1 – Control Register
• SSPSTAT – STATUS register
• SSPBUF – Serial Receive/Transmit Buffer
• SSPSR – Shift Register (Not directly accessible)
SSPCON1 and SSPSTAT are the control and STA-
TUS registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1:
DS41303G-page 194
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
SMP
Polarity of clock state is set by the CKP bit of the SSPCON1 register.
REGISTERS
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1 = Output data changes on clock transition from active to idle
0 = Output data changes on clock transition from idle to active
D/A: Data/Address bit
Used in I
P: Stop bit
Used in I
S: Start bit
Used in I
R/W: Read/Write Information bit
Used in I
UA: Update Address bit
Used in I
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
R/W-0
CKE
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
2
2
2
2
2
C mode only.
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
C mode only.
C mode only.
C mode only.
W = Writable bit
‘1’ = Bit is set
R-0
D/A
(1)
R-0
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPSR is the shift register used for shifting data in
and out. SSPBUF provides indirect access to the
SSPSR register. SSPBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
R-0
S
transmission,
R/W
R-0
 2010 Microchip Technology Inc.
x = Bit is unknown
the
R-0
UA
SSPBUF
R-0
BF
is
bit 0
not