PIC18F43K20-E/MV Microchip Technology, PIC18F43K20-E/MV Datasheet - Page 33

• Manufacturer Part Number: PIC18F43K20-E/MV
• Description: 8KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TUB
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F43K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

2.5.2.1
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the TUN<5:0> bits of
the OSCTUNE register (Register 2-2).
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
REGISTER 2-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-0
Note 1:
INTSRC
R/W-0
The PLLEN bit is active only when the HFINTOSC is the primary clock source (FOSC<2:0> = 100X) and
the selected frequency is 8 MHz or 16 MHz. Otherwise, the PLLEN bit is unavailable and always reads ‘0’.
OSCTUNE Register
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)
0 = 31 kHz device clock derived directly from LFINTOSC internal oscillator
PLLEN: Frequency Multiplier PLL for HFINTOSC Enable bit
1 = PLL enabled for HFINTOSC (8 MHz and 16 MHz only)
0 = PLL disabled
TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110 =
000001 =
000000 = Oscillator module is running at the factory calibrated frequency.
111111 =
100000 = Minimum frequency
• • •
• • •
PLLEN
R/W-0
OSCTUNE: OSCILLATOR TUNING REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
R/W-0
TUN5
R/W-0
TUN4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock Mon-
itor (FSCM) and peripherals, are not affected by the
change in frequency.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.2.3 “Low Frequency Selection”.
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes. For more
details about the function of the PLLEN bit see
Section 2.6.2 “PLL in HFINTOSC Modes”
TUN3
PIC18F2XK20/4XK20
(1)
R/W-0
TUN2
x = Bit is unknown
R/W-0
TUN1
DS41303G-page 33
R/W-0
TUN0
bit 0