MCP4728T-E/UN Microchip Technology, MCP4728T-E/UN Datasheet - Page 4

Quad, 12-bit NV DAC With I2C Interface 10 MSOP 3x3mm T/R

MCP4728T-E/UN

Manufacturer Part Number
MCP4728T-E/UN
Description
Quad, 12-bit NV DAC With I2C Interface 10 MSOP 3x3mm T/R
Manufacturer
Microchip Technology
Datasheet

Specifications of MCP4728T-E/UN

Settling Time
6µs
Number Of Bits
12
Data Interface
I²C
Number Of Converters
4
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP4728EV - BOARD EVAL 12BIT 4CH DAC MCP4728
Power Dissipation (max)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCP4728T-E/UN
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
MCP4728T-E/UN
0
MCP4728
ELECTRICAL CHARACTERISTICS (CONTINUED)
DS22187E-page 4
Electrical Specifications: Unless otherwise indicated, all parameters apply at V
R
Power-on Reset
Threshold Voltage
Power-Up Ramp Rate
DC Accuracy
Resolution
Integral Nonlinearity (INL)
Error
DNL Error
Offset Error
Offset Error Drift
Gain Error
Gain Error Drift
Internal Voltage Reference (V
Internal Voltage Reference
Temperature Coefficient
Reference Output Noise
Output Noise Density
1/f Corner Frequency
Note 1:
L
= 5 kΩ, C
2:
3:
4:
5:
6:
7:
8:
9:
Parameter
All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.
The power-up ramp rate measures the rise of V
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
Test code range: 100 - 4000 codes, V
Time delay to settle to a new reference when switching from external to internal reference or vice versa.
This parameter is indirectly tested by Offset and Gain error testing.
Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
This time delay is measured from the falling edge of ACK pulse in I
This time delay is not included in the output settling time specification.
L
= 100 pF, G
X
= 1, T
ΔV
ΔV
f
Symbol
ΔG
CORNER
V
E
e
V
V
REF
DNL
V
RAMP
REF
INL
NREF
NREF
OS
G
POR
REF
n
E
OS
A
E
/°C
/°C
),
= -40°C to +125°C. Typical values are at +25°C, V
/°C
(Note
2.007
-0.75
-1.25
Min
3)
12
1
REF
Typical
2.048
±0.16
±0.44
0.25
0.09
±0.2
= V
125
290
400
2.2
0.4
1.2
1.0
±2
45
-3
5
DD
DD
, V
DD
over time.
+1.25
±0.75
2.089
Max
±13
20
= 5.5V.
ppm/°C -40 to 0°C
LSB/°C
ppm/°C 0 to +125°C
ppm/°C -45°C to +25°C
ppm/°C +25°C to +125°C
ppm/°C
LSB/°C
µV
μV
Units
% of
FSR
Hz
LSB
LSB
Bits
V/s
mV
V
V
p-p
H
2
Z
C command to the beginning of V
DD
All circuits, including EEPROM, are
ready to operate.
Note
Code Change: 000h to FFFh
Note 5
Note 5
Code = 000h
See
Code = FFFh,
Offset error is not included.
Typical value is at room
temperature
See
Code = FFFh,
0.1 – 10 Hz, G
Code = FFFh, 1 kHz, G
Code = FFFh, 10 kHz, G
= +2.7V to 5.5V, V
IH
Figure 2-24
Figure 2-25
© 2010 Microchip Technology Inc.
2,
= V
Note 4
DD
Conditions
, V
x
IL
= 1
= V
SS.
SS
= 0V,
x
x
= 1
= 1
OUT
.

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