PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 40

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

External Reset Input
At the RST input an external reset can be applied forcing the T-SMINT
state. This external reset signal is additionally fed to the RSTO output.
After release of an external reset, the C has to wait for min. t
write access to the T-SMINT
Reset Ouput
If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by
t
Reset Generation
The T-SMINT
and Under Voltage Detection (UVD) circuit (see
external components.
The POR/UVD circuit can be disabled via pin VDDDET.
The requirements on V
Chapter
Clocks and Data Lines During Reset
During reset the data clock (DCL), the bit clock (BCL), the microcontroller clock
and the frame synchronization (FSC) keep running.
During reset DD and DU are high; with the exception of:
• The output C/I code from the U-Transceiver on DD IOM
• The output C/I code from the S-Transceiver on DU IOM
1)
Data Sheet
DEACT
(Value after reset of register UCIR = ’00
during a Power-On/UVD Reset, the microcontroller clock MCLK is not running, but starts running as soon as
timer t
(see
DEAC
5.6.5.
is started.
Table
â
IX has an on-chip reset generator based on a Power-On Reset (POR)
42).
DD
â
IX (see
ramp-up during power-on reset are described in
Table
H
26
’)
41).
Table
42). The POR/UVD requires no
â
â
-2 channel 1 is ’TIM’ = 0000.
-2 channel 0 is ’DR’ = 0000
Functional Description
C
before it starts read or
â
IX in the reset
PEF 81902
2001-11-12
1)
(MCLK)