PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 193

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

SWAP
4.7.4
S_CR
Value after reset: FF
CI_CS
EN_D
EN_B2R
Data Sheet
7
1
This bit is used to select the IOM channel to which the S-transceiver C/I-
channel is related to.
Swap Inputs
0 =
1 =
S_CR - Control Register S-Transceiver Data
C/I Channel Selection
0 =
1 =
Enable Transceiver D-Channel Data
0 =
1 =
Enable Transceiver B2 Receive Data (transmitter receives from IOM)
0 =
CI_CS
The time slot and data port for the input of the CDAxy register is
defined by its own TSDPxy register. The data port for the CDAxy
input is vice versa to the output setting for CDAxy.
The input (time slot and data port) of the CDAx0 is defined by the
TSDP register of CDAx1 and the input of CDAx1 is defined by the
TSDP register of CDAx0. The data port for the CDAx0 input is vice
versa to the output setting for CDAx1. The data port for the CDAx1
input is vice versa to the output setting for CDAx0. The input
definition for time slot and data port CDAx0 are thus swapped to
CDAx1 and for CDAx1 to CDAx0. The outputs are not affected by
the SWAP bit.
C/I-channel in IOM-channel 0
C/I-channel in IOM-channel 1
The corresponding data path to the transceiver is disabled
The corresponding data path to the transceiver is enabled.
The corresponding data path to the transceiver is disabled
H
EN_D
EN_B2R EN_B1R EN_B2X EN_B1X
read/write
179
Register Description
Address:
PEF 81902
2001-11-12
D_CS
0
51
H