PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 162

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Each interrupt source in the ISTAH register can be selectively masked by setting the
corresponding bit in MASKH to ‘1’. Masked interrupt status bits are not indicated when
ISTAH is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ‘0’.
Bit 0..7
4.4.5
STAR
Value after reset: 40
XDOV
XFW
RACI
Data Sheet
XDOV
RME
7
7
Mask Bits
0 =
1 =
STAR - Status Register
Transmit Data Overflow
0 =
1 =
Transmit FIFO Write Enable
0 =
1 =
Receiver Active Indication
0 =
XFW
RPF
6
6
interrupt active
interrupt masked
No transmit data overflow
More than the selected block size of 16 or 32 bytes have been
written into the XFIFO, i.e. data has been overwritten.
Data can not be written in the XFIFO
Data can be written in the XFIFO. This bit may be polled instead of
(or in addition to) using the XPR interrupt.
The HDLC receiver is not active
H
RFO
r(0)
5
5
XPR
r(0)
4
4
read
148
RACI
XMR
3
3
XDU
r(0)
2
2
Register Description
XACI
Address:
1
0
1
PEF 81902
2001-11-12
0
0
0
0
21
H