PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 113

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

•
Figure 43
Data Sheet
EXMR.RFBS=11
so after the first 4
bytes of a new frame
have been stored in the
fifo a receive pool full
interrupt ISTAH.RPF
is set.
The HDLC
receiver has
written further
data into the FIFO.
When a frame
is complete, a
status byte (RSTA)
is appended.
Meanwhile two
more short frames
have been
received.
FIFO.
HDLC
Receiver
HDLC
Receiver
When the RFACC detects 16 valid bytes,
it sets a RPF interrupt. The µP reads the 16 bytes
and acknowledges the transfer by setting CMDR.RMC.
This causes the space occupied by the 16 bytes being
released.
RFIFO Operation
RAM
RAM
RSTA
RSTA
RSTA
µP
µP
32
16
32
16
8
4
8
RFIFO ACCESS
RFIFO ACCESS
CONTROLLER
CONTROLLER
RFBS=01
RFBS=11
RFACC
RFACC
99
The µP has read
the 4 bytes, sets
RFBS=01 (16 bytes)
and completes the
block transfer by
a CMDR.RMC command.
Following CMDR.RMC
the 4 bytes of the
last block are
deleted.
RMC
EXMR.RFBS=01
RMC
Receiver
HDLC
Receiver
HDLC
After the RMC acknowledgement the
RFACC detects a RSTA byte, i.e. end of
the frame, therefore it asserts
a RME interupt and increments the
RBC counter by 2.
RAM
RAM
Functional Description
RSTA
RSTA
RSTA
32
16
32
16
µP
8
4
8
RFIFO ACCESS
RFIFO ACCESS
CONTROLLER
CONTROLLER
PEF 81902
RFBS=01
RFBS=01
RFACC
RFACC
2001-11-12