PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 164

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

XME
XRES
All of these bits must not be set twice within one BCL clock cycle.
Note: After a XPR interrupt further data has to be written to the XFIFO and the
4.4.7
MODEH
Value after reset: C0
Data Sheet
appropriate Transmit Command (XTF) has to be written to the CMDR register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAH).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically except in extended transparent mode.
MDS2
7
1 =
Transmit Message End
0 =
1 =
Transmitter Reset
0 =
1 =
MODEH - Mode Register HDLC Controller
MDS1
After having written up to 16 or 32 bytes (EXMR.XFBS) in the
XFIFO, the microcontroller initiates the transmission of a
transparent frame by setting this bit to ‘1’. The opening flag is
automatically added to the message by the T-SMINT
the extended transparent mode.
inactive
By setting this bit to ‘1’ the microcontroller indicates that the data
block written last in the XFIFO completes the corresponding frame.
The T-SMINT
CRC (if XCRC = 0) and the closing flag sequence to the data except
in the extended transparent mode.
inactive
HDLC transmitter is reset and the XFIFO is cleared of any data.
This command can be used by the microcontroller to abort a frame
currently in transmission.
H
MDS0
â
IX completes the transmission by appending the
r(0)
read/write
150
RAC
DIM2
Register Description
DIM1
Address:
â
IX except in
PEF 81902
2001-11-12
DIM0
0
22
H