AM79C972BKI\W AMD (ADVANCED MICRO DEVICES), AM79C972BKI\W Datasheet - Page 85

• Manufacturer Part Number: AM79C972BKI\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BKI\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

When the software determines that the signal came
from the PCnet-FAST+ device, it writes to the device’s
PMCSR to put the device into power state D0. The soft-
ware then writes a 0 to the PME_STATUS bit to clear
the bit and turn off the PME signal, and it calls the de-
vice’s software driver to tell it that the device is now in
sta te D0. The sy st em s oftwar e c an c lea r th e
PME_STATUS bit either before, after, or at the same
time that it puts the device back into the D0 state.
Link Change Detect
Link change detect is one of Wake-up events defined
by the OnNow specification and is supported by the
RWU mode. Link Change Detect mode is set when the
LCMODE bit (CSR116, bit 8) is set either by software
or loaded through the EEPROM.
Link Change
MPPEN
PG
MPMODE
MPEN
LCMODE
Pattern
Input
BCR47
Pattern Match RAM (PMR)
BCR46
H_RESET
Magic Packet
Pattern Match
Link Change
Figure 48. OnNow Functional Diagram
MPDETECT
BCR45
Am79C972
R
S
POR
POR
SET
CLR
Q
Q
When this bit is set, any change in the Link status will
cause the LCDET bit (CSR116, bit 9) to be set. When
the LCDET bit is set, the RWU pin will be asserted and
the PME_STATUS bit (PMCSR register, bit 15) will be
set. If either the PME_EN bit (PMCSR, bit 8) or the
PME_EN_OVR bit (CSR116, bit 10) are set, then the
PME will also be asserted.
OnNow Pattern Match Mode
In the OnNow Pattern Match Mode, the PCnet-FAST+
compares the incoming packets with up to eight pat-
terns stored in the Pattern Match RAM (PMR). The
stored patterns can be compared with part or all of in-
coming packets, depending on the pattern length and
the way the PMR is programmed. When a pattern
match has been detected, then PMAT bit (CSR116, bit
7) is set. The setting of the PMAT bit causes the
S
R
S
R
S
R
POR
CLR
SET
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
MPMAT
LCDET
PMAT
PME_EN_OVR
LCEVENT
MPMAT
PME_EN
PME Status
POR
MPINT
LED
WUMI
S
R
RWU
DET
CLR
Q
Q
PME_STATUS
21485C-51
PME
85