AM79C972BKI\W AMD (ADVANCED MICRO DEVICES), AM79C972BKI\W Datasheet - Page 121

• Manufacturer Part Number: AM79C972BKI\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BKI\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

14
13
12-9
8-7 PORTSEL[1:0] Port Select bits allow for software
6
DRCVBC
DRCVPA
RES
INTL
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Cleared by H_RESET or
S_RESET and is unaffected by
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Disable
When
Am79C972 controller from re-
ceiving
Used for protocols that do not
support broadcast addressing,
except as a function of multicast.
DRCVBC is cleared by activation
of
(broadcast messages will be re-
ceived) and is unaffected by
STOP.
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the Am79C972 controller
will be disabled. Frames ad-
dressed to the nodes individual
physical address will not be rec-
ognized.
Reserved locations. Written as
zeros and read as undefined.
controlled selection of the net-
work medium. The only legal val-
ues for this field are 11 and 10.
A value of 11 selects the MII port
and a value of 10 selects the
GPSI port.
Internal Loopback. See the de-
scription of LOOP (CSR15, bit 2).
H_RESET
broadcast
set,
Receive
disables
or
messages.
Broadcast.
S_RESET
Am79C972
the
5
4
3
DRTY
FCOLL
DXMTFCS Disable Transmit CRC (FCS).
to 1, the Am79C972 controller will
attempt only one transmission. In
this mode, the device will not pro-
tect the first 64 bytes of frame
data in the Transmit FIFO from
being overwritten, because auto-
matic retransmission will not be
necessary. When DRTY is set to
0, the Am79C972 controller will
attempt 16 transmissions before
signaling a retry error.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
the collision logic to be tested.
The Am79C972 controller must
be in internal loopback for FCOLL
to be valid. If FCOLL = 1, a colli-
sion will be forced during loop-
back
which will result in a Retry Error.
If FCOLL = 0, the Force Collision
logic will be disabled. FCOLL is
defined after the initialization
block is read.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
When DXMTFCS is set to 0, the
transmitter will generate and ap-
pend an FCS to the transmitted
frame. When DXMTFCS is set to
1, no FCS is generated or sent
with
DXMTFCS is overridden when
ADD_FCS and ENP bits are set
in TMD1.
bit11) is set to 1, the setting of
DXMTFCS has no effect on
frames shorter than 64 bytes.
If
ADD_FCS is clear for a particular
frame, no FCS will be generated.
If ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in TMD1.
Disable Retry. When DRTY is set
Force Collision. This bit allows
When APAD_XMT bit (CSR4,
DXMTFCS
the
transmission
transmitted
is
set
attempts,
frame.
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