AM79C972BKI\W AMD (ADVANCED MICRO DEVICES), AM79C972BKI\W Datasheet - Page 27

• Manufacturer Part Number: AM79C972BKI\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BKI\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

DETAILED FUNCTIONS
Slave Bus Interface Unit
The slave bus interface unit (BIU) controls all accesses
to the PCI configuration space, the Control and Status
Registers (CSR), the Bus Configuration Registers
(BCR), the Address PROM (APROM) locations, and
the Expansion ROM. Table 2 shows the response of
the Am79C972 controller to each of the PCI commands
in slave mode.
Slave Configuration Transfers
The host can access the Am79C972 PCI configuration
space with a configuration read or write command. The
Am79C972 controller will assert DEVSEL during the
address phase when IDSEL is asserted, AD[1:0] are
both 0, and the access is a configuration cycle. AD[7:2]
C[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration
Read
Configuration
Write
Memory Read
Multiple
Dual Address
Cycle
Memory Read
Line
Memory Write
Invalidate
Table 2. Slave Commands
Use
Not used
Not used
Read of CSR, BCR, APROM,
and Reset registers
Write to CSR, BCR, and
APROM
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers
Read of the Expansion Bus
Memory mapped I/O write of
CSR, BCR, and APROM
Read of the Configuration
Space
Write to the Configuration
Space
Aliased to Memory Read
Not used
Aliased to Memory Read
Aliased to Memory Write
Am79C972
select the DWord location in the configuration space.
The Am79C972 controller ignores AD[10:8], because it
is a single function device. AD[31:11] are don’t care.
The active bytes within a DWord are determined by the
byte enable signals. Eight-bit, 16-bit, and 32-bit trans-
fers are supported. DEVSEL is asserted two clock cy-
c le s af ter t he ho s t h as as s e r te d F R AM E . A ll
c on fi gu rat io n c y c l es a re o f fi xe d le ng th . T h e
Am79C972 controller will assert TRDY on the third
clock of the data phase.
The Am79C972 controller does not support burst trans-
fers for access to configuration space. When the host
keeps FRAME asserted for a second data phase, the
Am79C972 controller will disconnect the transfer.
When the host tries to access the PCI configuration
space while the automatic read of the EEPROM after
H_RESET (see section on RESET) is on-going, the
Am79C972 controller will terminate the access on the
PCI bus with a disconnect/retry response.
The Am79C972 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardwired to 1. The Am79C972 controller
is capable of detecting a configuration cycle even when
its address phase immediately follows the data phase
of a transaction to a different target without any idle
state in-between. There will be no contention on the
DEVSEL, TRDY, and STOP signals, since the
Am79C972 controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
Slave I/O Transfers
After the Am79C972 controller is configured as an I/O
device by setting IOEN (for regular I/O mode) or
MEMEN (for memory mapped I/O mode) in the PCI
Command register, it starts monitoring the PCI bus for
access to its CSR, BCR, or APROM locations. If con-
figured for regular I/O mode, the Am79C972 controller
will look for an address that falls within its 32 bytes of I/
O address space (starting from the I/O base address).
The Am79C972 controller asserts DEVSEL if it detects
an address match and the access is an I/O cycle. If
configured for memor y mapped I/O mode, the
Am79C972 controller will look for an address that falls
within its 32 bytes of memory address space (starting
from the memory mapped I/O base address). The
Am79C972 controller asserts DEVSEL if it detects an
address match and the access is a memory cycle.
DEVSEL is asserted two clock cycles after the host has
asserted FRAME. See Figure 1 and Figure 2.
AD31
AD11
Don’t care
AD10
AD8
Don’t care
AD7
AD2
DWord
index
AD1
0
AD0
0
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