AM79C972BKI\W AMD (ADVANCED MICRO DEVICES), AM79C972BKI\W Datasheet - Page 118

• Manufacturer Part Number: AM79C972BKI\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BKI\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

7
6
5
118
MAPINT
MAPINTE
MCCINT
H_RESET and is not affected by
S_RESET or setting the STOP bit
When MAPINT is set to 1, INTA is
asserted if the enable bit MAP-
INTE is set to 1.
Read/Write accessible always.
MAPINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. MAPINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Read/Write accessible always.
MAPINTE
H_RESET and is not affected by
S_RESET or setting the STOP bit
When MCCINT is set to 1, INTA
is asserted if the enable bit MC-
CINTE is set to 1.
Read/Write accessible always.
MCCINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. MCCINT is cleared by
H_RESET and is not affected by
MII Management Auto-Poll Inter-
rupt. The MII Auto-Poll interrupt is
set by the Am79C972 controller
to indicate that the currently read
status does not match the stored
previous
change in state for the external
PHY. A change in the Auto-Poll
Access Method (BCR32, Bit 11)
will reset the shadow register and
will not cause an interrupt on the
first access from the Auto-Poll
section. Subsequent accesses
will generate an interrupt if the
shadow register and the read
register produce differences.
MII Auto-Poll Interrupt Enable. If
MAPINTE is set, the MAPINT bit
will be able to set the INTR bit.
MII
Complete Interrupt. The MII Man-
agement Command Complete In-
terrupt is set by the Am79C972
controller when a read or write
operation to the MII Data Port
(BCR34) is complete.
Management
status
is
set
indicating
to
Command
0
Am79C972
by
a
4
3
2
MCCINTE
MCCIINT
MCCIINTE MII
S_RESET or setting the STOP
bit.
Complete Interrupt Enable. If
MCCINTE is set to 1, the MC-
CINT bit will be able to set the
INTR bit when the host reads or
writes to the MII Data Port
(BCR34) only. Internal MII Man-
agement Commands will not gen-
erate an interrupt. For instance
Auto-Poll state machine generat-
ed MII management frames will
not generate an interrupt upon
completion unless there is a com-
pare error which get reported
through the MAPINT (CSR7, bit
6) interrupt or the MCCIINTE is
set to 1.
Read/Write accessible always.
MCCINTE
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Complete Internal Interrupt. The
MII
Complete Interrupt is set by the
Am79C972 controller when a
read or write operation on the MII
management port is complete
from an internal operation. Exam-
ples of internal operations are
Auto-Poll or MII Management
Port generated MII management
frames. These are normally hid-
den to the host.
When MCCIINT is set to 1, INTA
is asserted if the enable bit MC-
CINTE is set to 1.
Read/Write accessible always.
MCCIINT is cleared by the host
by writing a 1. Writing a 0 has no
effect. MCCIINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Complete Internal Interrupt En-
able. If MCCIINTE is set to 1, the
MCCIINT bit will be able to set
the INTR bit when the internal
state machines generate MII
MII
MII
Management
Management
Management
Management
is
set
to
Command
Command
Command
Command
0
by