AM79C972BKI\W AMD (ADVANCED MICRO DEVICES), AM79C972BKI\W Datasheet - Page 111

• Manufacturer Part Number: AM79C972BKI\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BKI\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

4
3
DXMT2PD Disable Transmit Two Part Defer-
EMBA
tries and begin periodic polling of
this entry. When the STP bit is
found to be true, and the descrip-
tor that contains this setting is
owned by the Am79C972 control-
ler, then the Am79C972 control-
ler will stop advancing through
the ring entries, store the descrip-
tor information that it has just
read, and wait for the next re-
ceive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
header portion of a receive pack-
et will always be written to a par-
ticular memory area, and the data
portion of a receive packet will al-
ways be written to a separate
memory area. The interrupt is
generated when the header bytes
have been written to the header
memory area.
Read/Write accessible always.
The LAPPEN bit will be reset to 0
by H_RESET or S_RESET and
will be unaffected by STOP.
See Appendix B for more infor-
mation on the Look Ahead Pack-
et Processing concept.
Read/Write accessible always.
DXMT2PD
H_RESET or S_RESET and is
not affected by STOP.
Read/Write accessible always.
EMBA is cleared by H_RESET or
S_RESET and is not affected by
STOP.
ral (see Medium Allocation sec-
tion
Management section for more
details). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
Enable Modified Back-off Algo-
rithm (see Contention Resolution
section in Media Access Man-
agement section for more de-
tails). If EMBA is set, a modified
back-off algorithm is implement-
ed.
in
the
is
Media
cleared
Access
Am79C972
by
2
1-0
BSWP
RES
choose between big and little En-
dian modes of operation. When
BSWP is set to a 1, big Endian
mode is selected. When BSWP is
set to 0, little Endian mode is se-
lected.
When big Endian mode is select-
ed, the Am79C972 controller will
swap the order of bytes on the AD
bus during a data phase on ac-
cesses to the FIFOs only. Specif-
ically, AD[31:24] becomes Byte
0, AD[23:16] becomes Byte 1,
AD[15:8] becomes Byte 2, and
AD[7:0] becomes Byte 3 when
big Endian mode is selected.
When little Endian mode is se-
lected, the order of bytes on the
AD bus during a data phase is:
AD[31:24] is Byte 3, AD[23:16] is
Byte 2, AD[15:8] is Byte 1, and
AD[7:0] is Byte 0.
Byte swap only affects data
transfers that involve the FIFOs.
Initialization block transfers are
not affected by the setting of the
BSWP bit. Descriptor transfers
are not affected by the setting of
the BSWP bit. RDP, RAP, BDP
and PCI configuration space ac-
cesses are not affected by the
setting of the BSWP bit. Address
PROM transfers are not affected
by the setting of the BSWP bit.
Expansion ROM accesses are
not affected by the setting of the
BSWP bit.
Note that the byte ordering of the
PCI bus is defined to be little En-
dian. BSWP should not be set to
1 when the Am79C972 controller
is used in a PCI bus application.
Read/Write accessible always.
BSWP is cleared by H_RESET or
S_RESET and is not affected by
STOP.
value of this bit is a 0. Writing a 1
to this bit has no effect on device
function. If a 1 is written to this bit,
then a 1 will be read back. Exist-
ing drivers may write a 1 to this bit
for compatibility, but new drivers
Byte Swap. This bit is used to
Reserved location. The default
111