AM79C972BKI\W AMD (ADVANCED MICRO DEVICES), AM79C972BKI\W Datasheet - Page 56

• Manufacturer Part Number: AM79C972BKI\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BKI\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

the message to arrive. It then decides whether to ac-
cept or reject the frame based on all active addressing
schemes. If the frame is accepted, the Am79C972 con-
troller checks the current receive buffer status register
CRST (CSR41) to determine the ownership of the cur-
rent buffer.
If ownership is lacking, the Am79C972 controller will
immediately perform a final poll of the current RDTE. If
ownership is still denied, the Am79C972 controller has
no buffer in which to store the incoming message. The
MISS bit will be set in CSR0 and the Missed Frame
Counter (CSR112) will be incremented. Another poll of
the current RDTE will not occur until the frame has fin-
ished.
If the Am79C972 controller sees that the last poll (ei-
ther a normal poll, or the final effort described in the
above paragraph) of the current RDTE shows valid
ownership, it proceeds to a poll of the next RDTE. Fol-
lowing this poll, and regardless of the outcome of this
poll, transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive de-
scriptor, the Am79C972 controller will continue to per-
form receive data DMA transfers to the first buffer. If the
frame length exceeds the length of the first buffer, and
the Am79C972 controller does not own the second
buffer, ownership of the current descriptor will be
passed back to the system by writing a 0 to the OWN
bit of RMD1. Status will be written indicating buffer
(BUFF = 1) and possibly overflow (OFLO = 1) errors.
If the frame length exceeds the length of the first (cur-
rent) buffer, and the Am79C972 controller does own
the second (next) buffer, ownership will be passed back
to the system by writing a 0 to the OWN bit of RMD1
when the first buffer is full. The OWN bit is the only bit
modified in the descriptor. Receive data transfers to the
second buffer may occur before the Am79C972 con-
troller proceeds to look ahead to the ownership of the
third buffer. Such action will depend upon the state of
the FIFO when the OWN bit has been updated in the
first descriptor. In any case, lookahead will be per-
formed to the third buffer and the information gathered
will be stored in the chip, regardless of the state of the
ownership bit.
This activity continues until the Am79C972 controller
recognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). The Am79C972 controller will subsequently up-
date the current RDTE status with the end of frame
(ENP) indication set, write the message byte count
(MCNT) for the entire frame into RMD2, and overwrite
the “current” entries in the CSRs with the “next” entries.
Receive Frame Queuing
The Am79C972 controller supports the lack of RDTEs
when SRAM (SRAM SIZE in BCR 25, bits 7-0) is en-
56
Am79C972
abled through the Receive Frame Queuing mecha-
nism. When the SRAM SIZE = 0, then the Am79C972
controller reverts back to the PCnet PCI II mode of op-
eration. This operation is automatic and does not re-
quire any programming by the host. When SRAM is
enabled, the Receive Frame Queuing mechanism
allows a slow protocol to manage more frames without
the high frame loss rate normally attributed to FIFO
based network controllers.
The Am79C972 controller will store the incoming
frames in the extended FIFOs until polling takes place;
if enabled, it discovers it owns an RDTE. The stored
frames are not altered in any way until written out into
system buffers. When the receive FIFO overflows, fur-
ther incoming receive frames will be missed during that
time. As soon as the network receive FIFO is empty, in-
coming frames are processed as normal. Status on a
per frame basis is not kept during the overflow process.
Statistic counters are maintained and accurate during
that time.
During the time that the Receive Frame Queuing mech-
anism is in operation, the Am79C972 controller relies
on the Receive Poll Time Counter (CSR 48) to control
the worst case access to the RDTE. The Receive Poll
Time Counter is programmed through the Receive Poll-
ing Interval (CSR49) register. The Received Polling In-
terval defaults to approximately 2 ms. The Am79C972
controller will also try to access the RDTE during nor-
mal descriptor accesses whether they are transmit or
receive accesses. The host can force the Am79C972
controller to immediately access the RDTE by setting
the RDMD (CSR 7, bit 13) to 1. Its operation is similar
to the transmit one. The polling process can be dis-
abled by setting the RXDPOLL (CSR7, bit 12) bit. This
will stop the automatic polling process and the host
must set the RDMD bit to initiate the receive process
into host memory. Receive frames are still stored even
when the receive polling process is disabled.
Software Interrupt Timer
The Am79C972 controller is equipped with a software
programmable free-running interrupt timer. The timer is
constantly running and will generate an interrupt STINT
(CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to
1. After generating the interrupt, the software timer will
load the value stored in STVAL and restart. The timer
value STVAL (BCR31, bits 15-0) is interpreted as an
unsigned number with a resolution of 256 Time Base
Clock periods. For instance, a value of 122 ms would
be programmed with a value of 9531 (253Bh), if the
Time Base Clock is running at 20 MHz. The default
value of STVAL is FFFFh which yields the approximate
maximum 838 ms timer duration. A write to STVAL re-
starts the timer with the new contents of STVAL.