AM79C972BKI\W AMD (ADVANCED MICRO DEVICES), AM79C972BKI\W Datasheet - Page 74

• Manufacturer Part Number: AM79C972BKI\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C972BKI\W

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

AS_EBOE
EBUA_EBA[7:0] are driven with the upper 8 bits of the
Expansion ROM address for one more clock cycle after
AS_EBOE goes low. Next, the Am79C972 controller
starts driving the lower 8 bits of the Expansion ROM
address on EBUA_EBA[7:0].
The time that the Am79C972 controller waits for data to
be valid is programmable. ROMTMG (BCR18, bits 15-
12) defines the time from when the Am79C972 control-
ler drives EBUA_EBA[7:0] with the lower 8 bits of the
Expansion ROM address to when the Am79C972 con-
The access time for the Expansion ROM or the EB-
DATA (BCR30) device (t
can be calculated by subtracting the clock to output
delay for the EBUA_EBA[7:0] outputs (t
subtracting the input to clock setup time for the
EBD[7:0] inputs (t
ROMTMG:
74
is
driven
s_D
) from the time defined by
ACC
Am79C972
high
Figure 39. Flash Configuration for the Expansion Bus
) during read operations
EBUA_EBA[7:0]
for
EBDA[15:8]
AS_/EBOE
EROMCS
EBD[7:0]
EBWE
one-half
v_A_D
) and by
clock,
Am79C972
troller latches in the data on the EBD[7:0] inputs. The
register value specifies the time in number of clock cy-
cles. When ROMTMG is set to nine (the default value),
EBD[7:0] is sampled with the next rising edge of CLK
ten clock cycles after EBUA_EBA[7:0] was driven with
a new address value. The clock edge that is used to
sample the data is also the clock edge that generates
the next Expansion ROM address. All four bytes of Ex-
pansion ROM data are stored in holding registers. One
clock cycle after the last data byte is available, the
Am79C972 controller asserts TRDY.
t
(t
The access time for the Expansion ROM or for the EB-
DATA (BCR30) device (t
can be calculated by subtracting the clock to output
delay for the EBUA EBA[7:0] outputs (t
ACC
D-FF
’374
s_D
)
= ROMTMG * CLK period *CLK_FAC - (t
A[23:16]
A[15:8]
A[7:0]
WE
DQ[7:0]
CS
OE
ACC)
FLASH
during write operations
v_A_D
21485C-42
) and by
v_A_D
) -