82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 8

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

List of Tables
Table 1: Operating Mode Selection ........................................................................................................................................................................... 23
Table 2: Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... 23
Table 3: Impedance Matching Value For The Receiver ............................................................................................................................................. 24
Table 4: Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... 26
Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4 .................................................................................................................................... 27
Table 6: Criteria Of Speed Adjustment Start .............................................................................................................................................................. 28
Table 7: Related Bit / Register In Chapter 3.6 ........................................................................................................................................................... 28
Table 8: Excessive Zero Error Definition ................................................................................................................................................................... 29
Table 9: LOS Condition In T1/J1 Mode ...................................................................................................................................................................... 31
Table 10: LOS Condition In E1 Mode .......................................................................................................................................................................... 31
Table 11: Related Bit / Register In Chapter 3.7 ........................................................................................................................................................... 32
Table 12: The Structure of SF ..................................................................................................................................................................................... 33
Table 13: The Structure of ESF ................................................................................................................................................................................... 34
Table 14: The Structure of T1 DM ............................................................................................................................................................................... 35
Table 15: The Structure of SLC-96 .............................................................................................................................................................................. 36
Table 16: Interrupt Source In T1/J1 Frame Processor ................................................................................................................................................ 38
Table 17: Related Bit / Register In Chapter 3.8.1 ........................................................................................................................................................ 39
Table 18: The Structure Of TS0 In CRC Multi-Frame .................................................................................................................................................. 43
Table 19: FAS/NFAS Bit/Pattern Error Criteria ............................................................................................................................................................ 44
Table 20: Interrupt Source In E1 Frame Processor ..................................................................................................................................................... 46
Table 21: Related Bit / Register In Chapter 3.8.2 ........................................................................................................................................................ 47
Table 22: Monitored Events In T1/J1 Mode ................................................................................................................................................................. 48
Table 23: Related Bit / Register In Chapter 3.9.1 ........................................................................................................................................................ 49
Table 24: Monitored Events In E1 Mode ..................................................................................................................................................................... 50
Table 25: Related Bit / Register In Chapter 3.9.2 ........................................................................................................................................................ 51
Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria ......................................................................................................................................... 52
Table 27: Related Bit / Register In Chapter 3.10.1 ...................................................................................................................................................... 53
Table 28: Related Bit / Register In Chapter 3.10.2 ...................................................................................................................................................... 54
Table 29: Related Bit / Register In Chapter 3.11.1 ...................................................................................................................................................... 55
Table 30: Interrupt Summarize In HDLC Mode ........................................................................................................................................................... 56
Table 31: Related Bit / Register In Chapter 3.11.2 ...................................................................................................................................................... 57
Table 32: Related Bit / Register In Chapter 3.12 ......................................................................................................................................................... 58
Table 33: Related Bit / Register In Chapter 3.13 ......................................................................................................................................................... 58
Table 34: Related Bit / Register In Chapter 3.14 ......................................................................................................................................................... 59
Table 35: Related Bit / Register In Chapter 3.15 ......................................................................................................................................................... 61
Table 36: A-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 62
Table 37: µ-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 62
Table 38: Related Bit / Register In Chapter 3.16 ......................................................................................................................................................... 63
Table 39: Operating Modes Selection In T1/J1 Receive Path ..................................................................................................................................... 64
Table 40: Operating Modes Selection In E1 Receive Path .......................................................................................................................................... 69
Table 41: Related Bit / Register In Chapter 3.17 ......................................................................................................................................................... 70
Table 42: Operating Modes Selection In T1/J1 Transmit Path .................................................................................................................................... 71
Table 43: Operating Modes Selection In E1 Transmit Path ......................................................................................................................................... 76
Table 44: Related Bit / Register In Chapter 3.18 ......................................................................................................................................................... 77
Table 45: Related Bit / Register In Chapter 3.19 ......................................................................................................................................................... 78
Table 46: Related Bit / Register In Chapter 3.20.1.1 ................................................................................................................................................... 80
Table 47: E1 Frame Generation .................................................................................................................................................................................. 81
Table 48: Control Over E Bits ...................................................................................................................................................................................... 81
List of Tables
8
August 20, 2009