82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 58

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
3.12
format in T1/J1 mode.
the F-bit in the ESF format (refer to Table 13). The six ‘X’s represent the
message. The BOM is declared only when the pattern is matched and
the received message is identical 4 out of 5 consecutive times or 8 out of
10 consecutive times and differs from the previous message. The identi-
fication time is selected by the AVC bit. After a new BOM is declared, the
message is loaded into the BOC[5:0] bits. Every time when the BOC[5:0]
bits are updated, it will be indicated by the BOCI bit. A ‘1’ in the BOCI bit
means there is an interrupt. The interrupt will be reported by the INT pin
if the BOCE bit is ‘1’.
to timing recovery, the incoming line can carry Synchronization Status
Messages, or SSM, to indicate the quality level of the incoming clock.
SSM (in code words) are transmitted and/or received through the data
link bits (DS1 ESF formats) in T1/J1 mode. XBOC[5:0] and BOC[5:0]
mode can be used to transmit and receive the code words of SSM,
respectively. In E1 mode, Sa bits in Time Slot 0 can be used for transmit
or receive SSM code words.
received codeword in SSM application. The XBOC[5:0] bits, on the other
hand, can be used to transmit the SSM codeword to the network far end.
pose. For example, if the Sa[4] bit is used in transmit direction, SSM is
transmitted by using the Sa[4] bit; in receive direction, the E1 Sa4 Code-
word Register contains the received SSM codeword.
Functional Description
Table 32: Related Bit / Register In Chapter 3.12
XBOC[5:0]
BOC[5:0]
Sa4[1:4]
The Bit-Oriented Message (BOM) can only be received in the ESF
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
In BITS application, network timing recovery is required. In addition
In T1/J1 ESF mode, the BOC[5:0] bits can be used to hold the
In E1 mode, each of the Sa[4:8] bits can be used for the same pur-
Sa[4:8]
BOCE
BOCI
AVC
Bit
BIT-ORIENTED MESSAGE RECEIVER
E1 TS0 International / National
BOC Interrupt Indication
T1/J1 XBOC Code
E1 Sa4 Codeword
BOC Control
RBOC Code
Register
T1/J1 Address (Hex)
081
083
082
080
054
056
58
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.13
ONLY)
deactivate codes only in framed or unframed T1/J1 data stream, and
meets ANSI T1.403 9.3.1.
deactivate code whose length and content are programmed in the
ASEL[1:0]/DSEL[1:0] bits and the ACT[7:0]/DACT[7:0] bits respectively.
In framed mode, the F-bit is selected by the IBCDIDLE bit to compare
with the target activate/deactivate code or not. In unframed mode, all
193 bits are compared with the target activate/deactivate code.
in the received data stream, the Inband Loopback Code Detector keeps
on monitoring the bit error, i.e., the bit differs from the target activate/
deactivate code. If in more than 126 consecutive 39.8ms fixed periods,
less than 600 bit errors are detected in each 39.8ms, the activate/deacti-
vate code is detected and the corresponding LBA/LBD bit will indicate it.
Once more than 600 bit errors are detected in a 39.8ms fixed period, the
activate/deactivate code is out of synchronization and the corresponding
LBA/LBD bit will be cleared. However, even if the F-bit is compared,
whether it is matched or not, the result will not cause bit errors, that is,
the comparison result of the F-bit is discarded.
will set the LBAI/LBDI bit, which means there is an interrupt. The inter-
rupt will be reported by the INT pin if the corresponding LBAE/LBDE bit
is set to ‘1’.
Table 33: Related Bit / Register In Chapter 3.13
The Inband Loopback Code Detector tracks the loopback activate/
The received data stream is compared with the target activate/
After four consecutive correct activate/deactivate codes are found
Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LBA/LBD bit
DSEL[1:0]
IBCDIDLE
DACT[7:0]
ASEL[1:0]
ACT[7:0]
LBAE
LBDE
LBAI
LBDI
LBA
LBD
Bit
INBAND LOOPBACK CODE DETECTOR (T1/J1
IBCD Detector Configuration
IBCD Interrupt Indication
IBCD Deactivate Code
IBCD Interrupt Control
IBCD Detector Status
IBCD Activate Code
Register
T1/J1 Address (Hex)
August 20, 2009
07B
07A
076
078
079
077