82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 28

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
3.6
selection is made by the RJA_E bit.
Figure 7.
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]
bits. Accordingly, the constant delay produced by the Jitter Attenuator is
16 bits, 32 bits or 64 bits. The 128-bit FIFO is used when large jitter tol-
erance is expected, while the 32-bit FIFO is used in delay sensitive
applications.
data stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter whose fre-
quency is lower than the CF passes through the DPLL without any atten-
uation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or 1.26
Hz, as selected by the RJA_BW bit. In E1 applications, the CF of the
DPLL can be 6.77 Hz or 0.87 Hz, as selected by the RJA_BW bit. The
lower the CF is, the longer time is needed to achieve synchronization.
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
RJA_IS bit. When the RJA_IS bit is ‘1’, an interrupt will be reported on
the INT pin if enabled by the RJA_IE bit.
enabled by setting the RJA_LIMT bit. When the JA-Limit function is
enabled, the speed of the outgoing data will be adjusted automatically if
the FIFO is close to its full or emptiness. The criteria of speed adjust-
ment start are listed in Table 6. Though the JA-Limit function can reduce
the possibility of FIFO overflow and underflow, the quality of jitter attenu-
ation is deteriorated.
Table 6: Criteria Of Speed Adjustment Start
Functional Description
Jittered Clock
Jittered Data
The Receive Jitter Attenuator can be chosen to be used or not. This
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
The FIFO is used as a pool to buffer the jittered input data, then the
The DPLL is used to generate a de-jittered clock to clock out the
If the incoming data moves faster than the outgoing data, the FIFO
To avoid overflow or underflow, the JA-Limit function can be
FIFO Depth
128 bits
32 bits
64 bits
RECEIVE JITTER ATTENUATOR
pointer
Figure 7. Jitter Attenuator
write
Criteria Of Speed Adjustment Start
32/64/128
DPLL
FIFO
2-bit close to full or empty
3-bit close to full or empty
4-bit close to full or empty
pointer
read
De-jittered Data
De-jittered Clock
28
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
read and write pointer of the FIFO or the peak-peak interval between the
read and write pointer of the FIFO can be indicated in the RJITT[6:0]
bits. When the RJITT_TEST bit is ‘0’, the current interval between the
read and write pointer of the FIFO will be written into the RJITT[6:0] bits.
When the RJITT_TEST bit is ‘1’, the current interval will be compared
with the old one in the RJITT[6:0] bits and the larger one will be indi-
cated by the RJITT[6:0] bits.
I.431, G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/
13, AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.10 Jitter Tolerance and Chapter 7.11 Jitter
Transfer for details.
Table 7: Related Bit / Register In Chapter 3.6
RJA_DP[1:0]
RJITT_TEST
RJA_LIMT
RJITT[6:0]
RJA_BW
RJA_IS
RJA_IE
RJA_E
Selected by the RJITT_TEST bit, the real time interval between the
The performance of Receive Jitter Attenuator meets the ITU-T
Bit
Receive Jitter Attenuation Configuration
Receive Jitter Measure Value Indication
Interrupt Enable Control 1
Interrupt Status 1
Register
August 20, 2009
Address (Hex)
03B
027
034
039