82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 19

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
Pin Description
GNDDIO[0]
GNDDIO[1]
GNDDIO[2]
VDDDIO[0]
VDDDIO[1]
VDDDIO[2]
VDDDC[0]
VDDDC[1]
VDDDC[2]
VDDDC[3]
GNDDC[0]
GNDDC[1]
GNDDC[2]
GNDDC[3]
GNDAR
GNDAX
GNDAP
GNDAB
VDDAR
GNDAT
VDDAX
VDDAP
VDDAB
VDDAT
SPIEN
Name
TRST
TMS
TDO
TCK
TDI
Ground
Ground
Ground
Ground
Ground
Ground
Ground
High-Z
Power
Power
Power
Power
Power
Power
Power
Type
Input
Input
Input
Input
Input
Pin No.
23
77
80
78
79
76
73
30
52
69
34
48
71
32
50
68
35
47
16
19
15
14
10
13
3
4
6
5
8
7
SPIEN: Serial Microprocessor Interface Enable
When this pin is low, the microprocessor interface is in parallel mode.
When this pin is high, the microprocessor interface is in SPI mode.
SPIEN is a Schmitt-trigger input.
TRST: Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. This pin is a Schmitt-triggered input with an internal pull-up resistor. It
must be connected to the RESET pin or ground when JTAG is not used.
TMS: Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TCK: Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is clocked
out of the device on the falling edge of TCK. This pin is a Schmitt-triggered input with an internal pull-up resistor.
TDI: Test Input
The test data is sampled at this pin on the rising edge of TCK. This pin has an internal pull-up resistor. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TDO: Test Output
The test data are output on this pin. It is updated on the falling edge of TCK. This pin is High-Z except during the process
of data scanning.
VDDDIO[2:0]: 3.3 V I/O Power Supply
GNDDIO[2:0]: Digital Pad Ground
VDDDC[3:0]: 1.8 V Digital Core Power Supply
GNDDC[3:0]: Digital Core Ground
VDDAR: 3.3 V Power Supply for Receiver
GNDAR: Analog Ground for Receiver
VDDAT: 3.3 V Power Supply for Transmitter
GNDAT: Analog Ground for Transmitter
VDDAX: 3.3 V Power Supply for Transmit Driver
GNDAX: Analog Ground for Transmitter Driver
VDDAP: 3.3 V Power Analog PLL
GNDAP: Analog Ground PLL
VDDAB: 3.3 V Power Analog Bias
GNDAB: Analog Ground Bias
JTAG (per IEEE 1149.1)
Power & Ground
19
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
August 20, 2009