82P2281PFG8 IDT, Integrated Device Technology Inc, 82P2281PFG8 Datasheet - Page 73

• Manufacturer Part Number: 82P2281PFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

pin and the framing pulse on the TSFS pin to input the data on the TSD
pin are provided by the system side. The signaling bits on the TSIG pin
are per-channel aligned with the data on the TSD pin.
is clocked by the TSCK. The active edge of the TSCK used to sample
the pulse on the TSFS is determined by the FE bit. The active edge of
the TSCK used to sample the data on the TSD and TSIG is determined
by the DE bit. If the FE bit and the DE bit are not equal, the pulse on the
TSFS is ahead. The data rate of the system side is 1.544 Mb/s or 2.048
Mb/s. When it is 2.048 Mb/s, the TSCK can be selected by the CMS bit
to be the same rate as the data rate on the system side (2.048 MHz) or
double the data rate (4.096 MHz). If the speed of the TSCK is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the TSD
and TSIG pins. The pulse on the TSFS pin is always sampled on its first
active edge.
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFS is selected by the FSINV bit. If the pulse on the TSFS pin is not an
integer multiple of 125 µ s, this detection will be indicated by the TCOFAI
bit. If the TCOFAE bit is enabled, an interrupt will be reported by the INT
pin when the TCOFAI bit is ‘1’.
3.18.1.3
rate on the system side (2.048 Mb/s) should be mapped to the data rate
in the line side (1.544 Mb/s), 3 kinds of schemes should be selected by
the MAP[1:0] bits. The schemes per G.802, per One Filler Every Four
CHs and per Continuous CHs are the same as the description in
Chapter 3.18.1.2 Transmit Clock Slave Mode.
transmit the data to the link. The data of the link is byte-interleaved input
from the multiplexed bus. When the data on the multiplexed bus is input
to the link, the position of the data is arranged by setting the channel off-
set.
IDT82P2281
1.544
2.048
Mb/s
Mb/s
discarded
In the Transmit Clock Slave mode, the timing signal on the TSCK
In the Transmit Clock Slave mode, the data on the system interface
In the Transmit Clock Slave mode, the TSFS can indicate each F-
In the Transmit Multiplexed mode, since the demultiplexed data
In the Transmit Multiplexed mode, one multiplexed bus is used to
Transmit Multiplexed Mode
TS0
the 8th bit
F
CH1
TS1
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode
CH2
TS2
TS3
CH3
TS23
CH23
TS24
73
CH24
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
pin and the framing pulse on the MTSFS pin are provided by the system
side. The signaling bits on the MTSIG pin are per-channel aligned with
the corresponding data on the MTSD pin.
is clocked by the MTSCK. The active edge of the MTSCK used to sam-
ple the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSD and MTSIG
is determined by the DE bit. If the FE bit and the DE bit are not equal,
the pulse on the MTSFS is ahead. The MTSCK can be selected by the
CMS bit to be the same rate as the data rate on the system side (8.192
MHz) or double the data rate (16.384 MHz). If the speed of the MTSCK
is double the data rate, there will be two active edges in one bit duration.
In this case, the EDGE bit determines the active edge to sample the
data on the MTSD and MTSIG pins. The pulse on the MTSFS pin is
always sampled on its first active edge.
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
MTSFS is selected by the FSINV bit. If the pulse on the MTSFS pin is
not an integer multiple of 125 µ s, this detection will be indicated by the
TCOFAI bit. If the TCOFAE bit is enabled, an interrupt will be reported by
the INT pin when the TCOFAI bit is ‘1’.
3.18.1.4
modes. The offset is between the framing pulse on the TSFS/MTSFS
pin and the start of the corresponding frame input on the TSD/MTSD
pin. The signaling bits on the TSIG/MTSIG pin are always per-channel
aligned with the data on the TSD/MTSD pin.
discarded
TS25~TS31
In the Transmit Multiplexed mode, the timing signal on the MTSCK
In the Transmit Multiplexed mode, the data on the system interface
In the Transmit Multiplexed mode, the MTSFS can indicate each F-
Bit offset and channel offset are both supported in all the operating
Figure 28 to Figure 31 show the base line without offset.
F
CH1
discarded
Offset
TS0
CH2
the 8th bit
TS1
TS2
CH24
August 20, 2009
F CH1
TS24