C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 42

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
5.1.
AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to
individual Port pins, the on-chip temperature sensor, or the positive power supply (V
input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the neg-
ative input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential
Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR
Definition 5.1 and SFR Definition 5.2.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers.
Inputs are measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justi-
fied and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-jus-
tified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a
Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See
Output” on page 142
42
VREF x 1023/1024
–VREF x 256/512
VREF x 512/1024
VREF x 256/1024
VREF x 256/512
VREF x 511/512
(Single-Ended)
Input Voltage
Input Voltage
(Differential)
Analog Multiplexer
–VREF
0
0
for more Port I/O configuration details.
Right-Justified ADC0H:ADC0L
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
(AD0LJST = 0)
0xFE00
0x01FF
0x0000
0xFF00
0x0100
0x03FF
0x0200
0x0100
0x0000
Rev. 1.3
Left-Justified ADC0H:ADC0L
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
(AD0LJST = 1)
Section “15. Port Input/
0xFFC0
0x7FC0
0xC000
0x8000
0x4000
0x0000
0x4000
0x0000
0x8000
DD
). The negative