C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 267

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

Bit7:
Bit6:
Bit5:
Bit4:
Bits3–1: CPS2–CPS0: PCA Counter/Timer Pulse Select.
Bit0:
Note: When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the
CIDL
R/W
Bit7
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 4 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 4 enabled as Watchdog Timer.
WDLCK: Watchdog Timer Lock
This bit enables and locks the Watchdog Timer. When WDLCK is set to ‘1’, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer unlocked.
1: Watchdog Timer enabled and locked.
UNUSED. Read = 0b, Write = don't care.
These bits select the timebase source for the PCA counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
*Note: External oscillator source divided by 8 is synchronized with the system clock.
CPS2
WDTE
0
0
0
0
1
1
1
1
R/W
Bit6
CPS1
WDLCK
SFR Definition 22.2. PCA0MD: PCA Mode
0
0
1
1
0
0
1
1
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
-
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8*
Reserved
Reserved
Rev. 1.3
CPS2
R/W
Bit3
CPS1
R/W
Bit2
Timebase
.
CPS0
R/W
Bit1
ECF
R/W
Bit0
SFR Address:
01000000
Reset Value
0xD9
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