C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 273

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

23.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming functions may be performed. This is possible because C2 communication is typically
performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
In this halted state, the C2 interface can safely ‘borrow’ the C2CK (RST) and C2D (P3.0) pins. Note that
the C2D pin is shared on the 32-pin packages only (C8051F342/3/6/7/9/A/B). In most applications, exter-
nal resistors are required to isolate C2 interface traffic from the user application. A typical isolation configu-
ration is shown in Figure 23.1.
The configuration in Figure 23.1 assumes the following:
Additional resistors may be necessary depending on the specific application.
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Output (c)
RST (a)
Input (b)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 23.1. Typical C2 Pin Sharing
C2 Interface Master
Rev. 1.3
C2CK
C2D
C8051Fxxx
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