C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 100

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
11. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source
Program execution begins at location 0x0000.
100
XTAL1
XTAL2
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
(Section “22.3. Watchdog Timer Mode” on page 264
Internal LF
Internal HF
Oscillator
Oscillator
Oscillator
Multiplier
External
Clock
Drive
Px.x
Px.x
Section “14. Oscillators” on page 131
System
Clock
DD
Clock Select
Monitor and Power-On Resets, the RST pin is driven low until the device
Comparator 0
Figure 11.1. Reset Sources
+
-
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
C0RSEF
CIP-51
Handler
Core
VDD
WDT
PCA
EN
Rev. 1.3
Supply
Monitor
+
-
System Reset
Enable
Software Reset (SWRSF)
Power On
for information on selecting and configuring
Reset
Operation
details the use of the Watchdog Timer).
FLASH
Errant
Controller
'0'
USB
(wired-OR)
Transition
VBUS
Reset
Funnel
RST