MT47H32M16HR-3 IT:F TR Micron Technology Inc, MT47H32M16HR-3 IT:F TR Datasheet - Page 99
![DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R](/photos/31/34/313419/mfg557-84-fbga_sml.jpg)
MT47H32M16HR-3 IT:F TR
Manufacturer Part Number
MT47H32M16HR-3 IT:F TR
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Specifications of MT47H32M16HR-3 IT:F TR
Density
512 Mb
Maximum Clock Rate
667 MHz
Package
84FBGA
Address Bus Width
15 Bit
Operating Supply Voltage
1.8 V
Maximum Random Access Time
0.45 ns
Operating Temperature
-40 to 85 °C
Organization
32Mx16
Address Bus
15b
Access Time (max)
450ps
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
250mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
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Figure 53: x4, x8 Data Output Timing –
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
DQ (first data no longer valid)
DQ (first data no longer valid)
All DQs and DQS collectively 6
DQ (last data valid)
DQ (last data valid)
Notes:
Earliest signal transition
Latest signal transition
DQS#
DQS 3
1.
2.
3. DQ transitioning after the DQS transition defines the
4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ0–DQ7 for x8.
5.
6. The data valid window is derived for each DQS transition and is defined as
CK#
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
CK
t
t
transitions, and ends with the last valid transition of DQ.
T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
T1
t HP 1
t
DQSQ,
t
CL or
t HP 1
t
HP:
t DQSQ 2
t
QH, and Data Valid Window
t QH 5
t
t
QH =
CH clock transitions collectively when a bank is active.
99
T2
window
Data
valid
T2
T2
T2
t HP 1
t
HP -
t DQSQ 2
T2n
t QHS
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t QH 5
QHS.
512Mb: x4, x8, x16 DDR2 SDRAM
window
t HP 1
T2n
Data
valid
T2n
T2n
T3
t DQSQ 2
t QH 5
t QHS
t HP 1
t
window
DQSQ window. DQS transitions at
Data
valid
T3
T3
T3
T3n
© 2004 Micron Technology, Inc. All rights reserved.
t DQSQ 2
t QHS
t QH 5
t HP 1
window
T4
Data
valid
T3n
T3n
T3n
t
QH -
t QHS
READ
t
DQSQ.
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