MT47H32M16HR-3 IT:F TR Micron Technology Inc, MT47H32M16HR-3 IT:F TR Datasheet - Page 10
![DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R](/photos/31/34/313419/mfg557-84-fbga_sml.jpg)
MT47H32M16HR-3 IT:F TR
Manufacturer Part Number
MT47H32M16HR-3 IT:F TR
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Specifications of MT47H32M16HR-3 IT:F TR
Density
512 Mb
Maximum Clock Rate
667 MHz
Package
84FBGA
Address Bus Width
15 Bit
Operating Supply Voltage
1.8 V
Maximum Random Access Time
0.45 ns
Operating Temperature
-40 to 85 °C
Organization
32Mx16
Address Bus
15b
Access Time (max)
450ps
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
250mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
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Automotive Temperature
General Notes
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
The automotive temperature (AT) option, if offered, has two simultaneous require-
ments: ambient temperature surrounding the device cannot be less than –40°C or
greater than +105°C, and the case temperature cannot be less than –40°C or greater
than +105°C. JEDEC specifications require the refresh rate to double when T
+85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T
+85°C.
• The functionality and the timing specifications discussed in this data sheet are for the
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
• Complete functionality is described throughout the document, and any page or dia-
• Any specific requirement takes precedence over a general statement.
DLL-enabled mode of operation.
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte.
For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the
upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS.
gram may have been simplified to convey a topic and may not be inclusive of all
requirements.
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description
© 2004 Micron Technology, Inc. All rights reserved.
C
is < 0°C or >
C
exceeds
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