MT47H32M16HR-3 IT:F TR Micron Technology Inc, MT47H32M16HR-3 IT:F TR Datasheet - Page 127
![DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R](/photos/31/34/313419/mfg557-84-fbga_sml.jpg)
MT47H32M16HR-3 IT:F TR
Manufacturer Part Number
MT47H32M16HR-3 IT:F TR
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Specifications of MT47H32M16HR-3 IT:F TR
Density
512 Mb
Maximum Clock Rate
667 MHz
Package
84FBGA
Address Bus Width
15 Bit
Operating Supply Voltage
1.8 V
Maximum Random Access Time
0.45 ns
Operating Temperature
-40 to 85 °C
Organization
32Mx16
Address Bus
15b
Access Time (max)
450ps
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
250mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
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MRS Command to ODT Update Delay
Figure 80: Timing for MRS Command to ODT Update Delay
Figure 81: ODT Timing for Active or Fast-Exit Power-Down Mode
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
Notes:
During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command.
R
Command
Command
TT
Address
Internal
1. The LM command is directed to the mode register, which updates the information in
2. To prevent any impedance glitch on the channel, the following conditions must be met:
setting
ODT 2
ODT
CK#
CKE
CK#
R
CK
CK
TT
EMR (A6, A2), that is, R
t
entire duration of the
AOFD must be met before issuing the LM command; ODT must remain LOW for the
Valid
Valid
T0
T0
Old setting
t AOFD
t CK
EMRS 1
Ta0
Valid
Valid
T1
t CH
0ns
t
TT
MOD window until
127
(nominal).
t CL
t AON (MIN)
t AOND
Ta1
NOP
Valid
Valid
t AON (MAX)
T2
t MOD
t
MOD (MAX) updates the R
Undefined
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
Ta2
Valid
Valid
T3
t AOFD
512Mb: x4, x8, x16 DDR2 SDRAM
R
TT
t
MOD is met.
Unknown
NOP
Ta3
Valid
Valid
T4
t IS
t AOF (MIN)
R
2
Ta4
NOP
Valid
Valid
TT
T5
© 2004 Micron Technology, Inc. All rights reserved.
t AOF (MAX)
On
New setting
Indicates a break in
time scale
TT
setting.
NOP
Ta5
Valid
Valid
Don’t Care
T6
ODT Timing
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