82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 85
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82V3280EQG
Manufacturer Part Number
82V3280EQG
Description
WAN PLL 100-Pin TQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of 82V3280EQG
Package
100TQFP
Operating Temperature
-40 to 85 °C
Available stocks
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Part Number
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Quantity
Price
Part Number:
82V3280EQG
Manufacturer:
IDT
Quantity:
20 000
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IN7_CNFG - Input Clock 7 Configuration
Programming Information
IDT82V3280
Address: 1BH
Type: Read / Write
Default Value: 00000011
DIRECT_DIV
5 - 4
3 - 0
Bit
7
6
7
BUCKET_SEL[1:0]
IN_FREQ[3:0]
DIRECT_DIV
LOCK_8K
Name
LOCK_8K
6
Refer to the description of the LOCK_8K bit (b6, 1BH).
This bit, together with the DIRECT_DIV bit (b7, 1BH), determines whether the DivN Divider or the Lock 8k Divider is used for
IN7:
These bits select one of the four groups of leaky bucket configuration registers for IN7:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN7:
0000: 8 kHz.
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz. (default)
0100: 25.92 MHz.
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For IN7, the required frequency should not be set higher than that of the input clock.
BUCKET_SEL1
DIRECT_DIV bit
5
0
0
1
1
BUCKET_SEL0
4
LOCK_8K bit
0
1
0
1
85
IN_FREQ3
3
Description
IN_FREQ2
2
Both bypassed (default)
Lock 8k Divider
Used Divider
DivN Divider
Reserved
IN_FREQ1
1
December 9, 2008
IN_FREQ0
0
WAN PLL
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