82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 147

• Manufacturer Part Number: 82V3280EQG
• Description: WAN PLL 100-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 82V3280EQG

• Package: 100TQFP
• Operating Temperature: -40 to 85 °C

PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2
Programming Information
IDT82V3280
Address:7BH
Type: Read / Write
Default Value: 0XXXXX00
PH_OFFSET_E
6 - 2
1 - 0
Bit
7
N
7
PH_OFFSET_EN
PH_OFFSET[9:8]
Name
-
6
-
This bit determines whether the input-to-output phase offset is enabled.
If the device is configured as the Master, the input-to-output phase offset:
0: Disabled. (default)
1: Enabled.
If the device is configured as the Slave, the input-to-output phase offset is always enabled.
Reserved.
These bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the input-to-output phase offset in ns
to adjust will be gotten.
5
-
4
-
147
3
-
Description
2
-
PH_OFFSET9
1
December 9, 2008
PH_OFFSET8
0
WAN PLL