82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 13
![no-image](/images/manufacturer_photos/0/3/333/integrated_device_technology__idt__sml.jpg)
82V3280EQG
Manufacturer Part Number
82V3280EQG
Description
WAN PLL 100-Pin TQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of 82V3280EQG
Package
100TQFP
Operating Temperature
-40 to 85 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
82V3280EQG
Manufacturer:
IDT
Quantity:
20 000
- Current page: 13 of 171
- Download datasheet (2Mb)
2
Table 1: Pin Description
Pin Description
IDT82V3280
SONET/SDH
FF_SRCSW
EX_SYNC1
IN5_POS
IN5_NEG
MS/SL
Name
OSCI
RST
IN1
IN2
IN3
IN4
PIN DESCRIPTION
Pin No.
100
10
18
99
74
45
24
25
46
47
40
41
pull-down
pull-down
pull-down
pull-down
pull-down
pull-up
pull-up
I/O
I
I
I
I
I
I
I
I
I
I
I
PECL/LVDS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
AMI
AMI
Frame Synchronization Input Signal
Global Control Signal
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH)
EXT_SW bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is
enabled);
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is dis-
abled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is
enabled:
High: Pair IN3 / IN5 is selected.
Low: Pair IN4 / IN6 is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, 13H), controls whether the device is config-
ured as the Master or as the Slave. Refer to
details.
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, 09H).
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
IN1: Input Clock 1
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN2: Input Clock 2
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN3: Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN4: Input Clock 4
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
Input Clock
13
3
3
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
Description
Chapter 3.14 Master / Slave Configuration
1
December 9, 2008
WAN PLL
2
. The
for
Related parts for 82V3280EQG
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![IDT%4841CP](/images/manufacturer_photos/0/3/334/integrated_device_technology__inc__tmb.jpg)
Part Number:
Description:
High-performance CMOS bus interface latches
Manufacturer:
Integrated Device Technology, Inc.
![IDT71024S17Y](/images/manufacturer_photos/0/3/334/integrated_device_technology__inc__tmb.jpg)
Part Number:
Description:
CMOS static RAM 1 meg (128K x 8-bit)
Manufacturer:
Integrated Device Technology, Inc.
Datasheet:
![IDT71V016S20YI](/images/manufacturer_photos/0/3/334/integrated_device_technology__inc__tmb.jpg)
Part Number:
Description:
IDT71V016S20YI3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)
Manufacturer:
Integrated Device Technology, Inc.
Datasheet: