82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 41

• Manufacturer Part Number: 82V3280EQG
• Description: WAN PLL 100-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 82V3280EQG

• Package: 100TQFP
• Operating Temperature: -40 to 85 °C

Table 25: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 APLL
Table 26: Outputs on OUT8 & OUT9
Functional Description
IDT82V3280
OUTn_DIVIDER[3:0]
Note:
1. 1 ≤ n ≤ 7. Each output is assigned a frequency divider.
2. In the APLL, the selected T0/T4 DPLL output may be multiplied. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is
reserved.
3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT6 and OUT7.
4. The 61.44 MHz, 30.72 MHz, 15.36 MHz, 7.68 MHz and 3.84 MHz outputs are only derived from T0 APLL.
OUT8_EN / OUT9_EN T4_INPUT_FAIL
(Output Divider)
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
0
1
1
77.76 MHz X 4 12E1 X 4
622.08 MHz
311.04 MHz
155.52 MHz
77.76 MHz
51.84 MHz
38.88 MHz
25.92 MHz
19.44 MHz
6.48 MHz
3
3
don’t-care
1
48E1
24E1
12E1
8E1
6E1
4E1
3E1
2E1
0
1
E1
/ T4_INPUT_FAIL
16E1 X 4
64E1
32E1
16E1
8E1
4E1
2E1
E1
outputs on OUT1 ~ OUT7 if derived from T0/T4 APLL output
2
24T1 X 4
96T1
48T1
24T1
16T1
12T1
8T1
6T1
4T1
3T1
2T1
T1
Output is disabled (output high).
Output is disabled (output low).
16T1 X 4
Output is disabled (output low) when the T4 selected input clock fails.
41
64T1
32T1
16T1
8T1
4T1
2T1
Output is enabled when the T4 selected input clock does not fail.
T1
E3
E3
Output is disabled (output low).
Outputs on OUT8 & OUT9
Output is enabled.
T3
T3
(26 MHz X 2)
52 MHz
26 MHz
13 MHz
GSM
2
(30.72 MHz X 10)
61.44 MHz
30.72 MHz
15.36 MHz
7.68 MHz
3.84 MHz
153.6 MHz
76.8 MHz
38.4 MHz
OBSAI
December 9, 2008
4
4
4
4
4
WAN PLL
(40 MHz)
20 MHz
10 MHz
5 MHz
GPS