82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 30

• Manufacturer Part Number: 82V3280EQG
• Description: WAN PLL 100-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 82V3280EQG

• Package: 100TQFP
• Operating Temperature: -40 to 85 °C

Table 14: Related Bit / Register in Chapter 3.8
3.8.2.2
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the highest priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smallest ‘n’ is selected.
3.8.3
CURRENTLY_SELECTED_INPUT[3:0] bits. Note if the T4 selected
input clock is a T0 DPLL output, it can not be indicated by these bits.
Functional Description
Note: * The setting in the 26 ~ 2C, 4E and 4F registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
IDT82V3280
In Non-Revertive switch, the T0 selected input clock is not switched
The
INn_NO_ACTIVITY_ALARM (14 ≥ n ≥ 1)
INn_FREQ_HARD_ALARM (14 ≥ n ≥ 1)
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
SECOND_PRIORITY_VALIDATED[3:0]
INn_SEL_PRIORITY[3:0] (14 ≥ n ≥ 1)
INn_PH_LOCK_ALARM (14 ≥ n ≥ 1)
THIRD_PRIORITY_VALIDATED[3:0]
selected
Non-Revertive Switch (T0 only)
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
T0_MAIN_REF_FAILED
T0_MAIN_REF_FAILED
INn_VALID (14 ≥ n ≥ 1)
LOS_FLAG_TO_TDO
IN_NOISE_WINDOW
REVERTIVE_MODE
INn
INn
INn
ULTR_FAST_SW
INPUT_TO_T4
INPUT_TO_T4
T0_FOR_T4
T4_T0_SEL
AMI1_LOS
AMI2_LOS
1
2
3
input
(14 ≥ n ≥ 1)
(14 ≥ n ≥ 1)
(14 ≥ n ≥ 1)
Bit
clock
1
2
1
2
is
indicated
IN1_IN2_SEL_PRIORITY_CNFG ~ IN13_IN14_SEL_PRIORITY_CNFG
REMOTE_INPUT_VALID1_CNFG, REMOTE_INPUT_VALID2_CNFG
INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG
by
the
INPUT_VALID1_STS, INPUT_VALID2_STS
INTERRUPTS1_STS, INTERRUPTS2_STS
30
cated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_
PRIORITY_VALIDATED[3:0]
_VALIDATED[3:0] bits respectively. If more than one input clock INn has
the same priority, the input clock with the smallest ‘n’ is indicated by the
HIGHEST_PRIORITY_VALIDATED[3:0] bits.
switch
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
INPUT_TO_T4
rupt will be generated.
INTERRUPTS2_ENABLE_CNFG
INTERRUPTS3_ENABLE_CNFG
IN1_IN2_STS ~ IN13_IN14_STS
The qualified input clocks with the three highest priorities are indi-
When the device is configured in Automatic selection and Revertive
When all the input clocks for T4 path changes to be unqualified, the
PHASE_MON_PBO_CNFG
PRIORITY_TABLE1_STS
PRIORITY_TABLE2_STS
T4_T0_REG_SEL_CNFG
T4_INPUT_SEL_CNFG
MON_SW_PBO_CNFG
INPUT_MODE_CNFG
INTERRUPTS3_STS
INTERRUPTS2_STS
INTERRUPTS3_STS
is
Register
enabled,
1
bit will be set. If the INPUT_TO_T4
the
bits
input
and
clock
the
indicated
December 9, 2008
THIRD_PRIORITY
2
bit is ‘1’, an inter-
Address (Hex)
26 ~ 2C *
43 ~ 49
4A, 4B
0D, 0E
4C, 4D
10, 11
4E *
4F *
WAN PLL
0B
51
0F
78
0E
0F
12
09
07
11
by
the