82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 78
![no-image](/images/manufacturer_photos/0/3/333/integrated_device_technology__idt__sml.jpg)
82V3280EQG
Manufacturer Part Number
82V3280EQG
Description
WAN PLL 100-Pin TQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT82V3280DQG8.pdf
(171 pages)
Specifications of 82V3280EQG
Package
100TQFP
Operating Temperature
-40 to 85 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
82V3280EQG
Manufacturer:
IDT
Quantity:
20 000
- Current page: 78 of 171
- Download datasheet (2Mb)
INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3
Programming Information
IDT82V3280
Address: 12H
Type: Read / Write
Default Value: 00X00000
EX_SYNC_ALARM
Bit
7
6
5
4
3
2
1
0
7
EX_SYNC_ALARM
INPUT_TO_T4
AMI2_VIOL
AMI1_VIOL
AMI2_LOS
AMI1_LOS
T4_STS
Name
-
T4_STS
6
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has
occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T4 DPLL locking status
changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’), i.e., when the T4_STS bit (b6, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when all the input clocks for T4 path
change to be unqualified, i.e., when the INPUT_TO_T4 bit (b4, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN2 has AMI violation, i.e., when the
AMI2_VIOL bit (b3, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN2 has LOS error, i.e., when the
AMI2_LOS bit (b2, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN1 has AMI violation, i.e., when the
AMI1_VIOL bit (b1, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN1 has LOS error, i.e., when the
AMI1_LOS bit (b0, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
5
-
INPUT_TO_T4
4
78
AMI2_VIOL
3
Description
AMI2_LOS
2
AMI1_VIOL
1
December 9, 2008
AMI1_LOS
0
WAN PLL
Related parts for 82V3280EQG
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![IDT%4841CP](/images/manufacturer_photos/0/3/334/integrated_device_technology__inc__tmb.jpg)
Part Number:
Description:
High-performance CMOS bus interface latches
Manufacturer:
Integrated Device Technology, Inc.
![IDT71024S17Y](/images/manufacturer_photos/0/3/334/integrated_device_technology__inc__tmb.jpg)
Part Number:
Description:
CMOS static RAM 1 meg (128K x 8-bit)
Manufacturer:
Integrated Device Technology, Inc.
Datasheet:
![IDT71V016S20YI](/images/manufacturer_photos/0/3/334/integrated_device_technology__inc__tmb.jpg)
Part Number:
Description:
IDT71V016S20YI3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)
Manufacturer:
Integrated Device Technology, Inc.
Datasheet: